公开(公告)号：US6103569A

公开(公告)日：2000-08-15

申请号：US459730

申请日：1999-12-13

申请人： Kok Hin Teo ,  Feng Chen ,  Lap Chan

发明人： Kok Hin Teo ,  Feng Chen ,  Lap Chan

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76895

摘要： A method for planarizing metal plugs for device interconnections. The process begins by providing a semiconductor structure with at least one device thereon. A dielectric layer is formed over the device and the semiconductor structure. A first barrier metal layer is formed on the dielectric layer, and a sacrificial oxide layer is formed on the first barrier metal layer. The sacrificial oxide layer, the first barrier metal layer, and the dielectric layer are patterned to form contact openings. A second barrier metal layer is formed over the semiconductor structure, and a metal contact layer is formed on the second barrier metal layer. The metal contact layer and the second barrier metal layer are planarized using a first chemical mechanical polishing process and the sacrificial oxide layer is removed. The metal contact layer and the first barrier metal layer are planarized using a second chemical mechanical polishing process.

摘要翻译： 用于平面化用于器件互连的金属插头的方法。 该过程开始于在其上提供至少一个装置的半导体结构。 在器件和半导体结构上形成介电层。 在介电层上形成第一阻挡金属层，在第一阻挡金属层上形成牺牲氧化物层。 牺牲氧化物层，第一阻挡金属层和电介质层被图案化以形成接触开口。 在半导体结构上形成第二阻挡金属层，在第二阻挡金属层上形成金属接触层。 使用第一化学机械抛光工艺对金属接触层和第二阻挡金属层进行平面化处理，并去除牺牲氧化物层。 使用第二化学机械抛光工艺将金属接触层和第一阻挡金属层平坦化。

公开(公告)号：US6100196A

公开(公告)日：2000-08-08

申请号：US396254

申请日：1999-09-15

申请人： Lap Chan ,  Jia Zhen Zheng

发明人： Lap Chan ,  Jia Zhen Zheng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002

摘要： A method for making copper interconnections in an integrated circuit is described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

摘要翻译： 描述了在集成电路中制造铜互连的方法。 该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。 通过两个阻挡层防止铜从连接器的扩散。 一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。 镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。 抛光。 由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

公开(公告)号：US5742088A

公开(公告)日：1998-04-21

申请号：US837486

申请日：1997-04-18

申请人： Yang Pan ,  Lap Chan ,  Ravi Sundaresan

发明人： Yang Pan ,  Lap Chan ,  Ravi Sundaresan

IPC分类号： H01L21/74 ,  H01L29/08 ,  H01L27/11 ,  H01L29/40

CPC分类号： H01L21/743

摘要： A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction. A doped glasseous layer is deposited overlying the patterned tungsten silicide/polysilicon layer and within the trench, then isotropically etched away until it remains only partially filling the trench. The substrate is oxidized to drive-in dopant from the doped glasseous layer within the trench into the surrounding substrate. Ions are implanted to form the planned source/drain region. Dopant is outdiffused from the second polysilicon layer to form the planned buried contact junction wherein the dopant surrounding the trench provides a conduction channel between the source/drain region and the adjoining buried contact junction.

摘要翻译： 描述了形成改进的埋入接点的新方法。 在半导体衬底的表面上提供覆盖栅极氧化硅的多晶硅层，并被蚀刻掉以提供到衬底的开口，其中将形成预定的埋入接触结。 第二掺杂多晶硅层和硅化钨层被沉积并图案化以提供栅极电极和覆盖在计划的埋入接触结上的触点，并提供到衬底的开口，其中将形成预定的源极/漏极区域邻接计划的埋入接触结 并且其中不在多晶硅接触处的多晶硅层的一部分保留为残留物。 残留物被蚀刻掉，由此在规划的源极/漏极区域和计划的埋入接触结的接合处将沟槽蚀刻到衬底中。 在图案化的硅化钨/多晶硅层上并在沟槽内沉积掺杂的硅酸盐层，然后各向同性地蚀刻掉，直到其仅部分地填充沟槽。 衬底被氧化成驱动掺杂剂从沟槽内的掺杂的玻璃质层进入周围的衬底。 植入离子以形成规划的源/漏区。 掺杂剂从第二多晶硅层向外扩散以形成计划的埋入接触结，其中围绕沟槽的掺杂剂在源极/漏极区域和相邻的掩埋接触结点之间提供导电沟道。

公开(公告)号：US5728621A

公开(公告)日：1998-03-17

申请号：US845870

申请日：1997-04-28

申请人： Jia Zhen Zheng ,  Charlie Wee Song Tay ,  Wei Lu ,  Lap Chan

发明人： Jia Zhen Zheng ,  Charlie Wee Song Tay ,  Wei Lu ,  Lap Chan

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A new method for forming planarized high quality oxide shallow trench isolation is described. A nitride layer overlying a pad oxide layer is provided over the surface of a semiconductor substrate. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate wherein there is at least one first wide nitride region between two of the isolation trenches and at least one second narrow nitride region between another two of the isolation trenches. A high density plasma (HDP) oxide layer is deposited over the nitride layer filling the isolation trenches wherein the HDP oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer and wherein the difference in step heights of the HDP oxide between the first region and a region overlying an isolation trench is a first height. A layer of spin-on-glass is coated over the HDP oxide layer wherein the difference in step heights of the spin-on-glass material between the first region and the region overlying an isolation trench is a second height smaller than the first height. The spin-on-glass layer and portions of the HDP oxide layer in the first region are etched away. The spin-on-glass layer and HDP oxide layer remaining are polished away wherein the substrate is planarized.

摘要翻译： 描述了形成平面化高质量氧化物浅沟槽隔离的新方法。 覆盖衬垫氧化物层的氮化物层设置在半导体衬底的表面上。 通过氮化物和衬垫氧化物层蚀刻多个隔离沟槽到半导体衬底中，其中在两个隔离沟槽之间存在至少一个第一宽氮化物区域和在另外两个隔离沟槽之间的至少一个第二窄氮化物区域。 在填充隔离沟槽的氮化物层上沉积高密度等离子体（HDP）氧化物层，其中HDP氧化物在宽氮化物层上的第一区域中更厚地沉积，并且在第二区域上更薄地沉积在窄氮化物层上，并且其中 在第一区域和覆盖隔离沟槽的区域之间的HDP氧化物的阶跃高度的差异是第一高度。 在HDP氧化物层上涂覆一层旋涂玻璃，其中在第一区域和覆盖隔离沟槽的区域之间的旋涂玻璃材料的阶梯高度的差异是比第一高度小的第二高度。 旋转玻璃层和第一区域中的HDP氧化物层的部分被蚀刻掉。 抛光剩余的旋涂玻璃层和HDP氧化物层，其中衬底被平坦化。

公开(公告)号：US5693178A

公开(公告)日：1997-12-02

申请号：US559050

申请日：1996-01-18

申请人： Lap Chan ,  Simon Chooi

发明人： Lap Chan ,  Simon Chooi

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L22/34

摘要： A microloading quantification apparatus is comprising a supporting substrate, a first bonding pad deposited upon the supporting substrate, a second bonding pad deposited upon the supporting substrate, and an etched conductive pattern deposited upon the supporting substrate and operably connected to the first bonding pad and the second bonding pad. Methods for the formation and application of the microloading quantification apparatus to quantify the variation of the microloading effect as a result of modifications of the set of parameters of integrated circuit processing particularly those of the plasma dry etch are described.

摘要翻译： 微量负载量化装置包括支撑衬底，沉积在支撑衬底上的第一焊盘，沉积在支撑衬底上的第二焊盘，以及沉积在支撑衬底上并可操作地连接到第一焊盘和 第二粘接垫。 描述了形成和应用微量负荷量化装置的方法，以量化由于集成电路处理的一组参数，特别是等离子体干蚀刻的参数组的修改而导致的微加载效应的变化。

公开(公告)号：US5627094A

公开(公告)日：1997-05-06

申请号：US566809

申请日：1995-12-04

申请人： Lap Chan ,  Yeow M. Teo

发明人： Lap Chan ,  Yeow M. Teo

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L27/06 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L28/40 ,  H01L21/76895 ,  H01L27/0629 ,  H01L27/108 ,  H01L28/60 ,  H01L28/82 ,  H01L28/90

摘要： A method for forming a stacked container capacitor for use within integrated circuits. Formed successively upon a semiconductor substrate is a first dielectric layer, a second dielectric layer and a patterned mask layer. Within an isotropic etch process, the first dielectric layer etches slower than the second dielectric layer. By means of an anisotropic etch process employing the patterned mask layer as a mask, an aperture is etched at least partially through the first dielectric layer. By means of an isotropic etch process employing the patterned mask layer as a mask, the second dielectric layer is etched to yield a ledge formed above the first dielectric layer and below the patterned masking layer. The patterned mask layer is then removed. Formed then into the anisotropically and isotropically etched aperture is a first polysilicon layer, a third dielectric layer and a second polysilicon layer. Finally, the filled isotropically etched aperture is planarized until there is exposed a flange of the first polysilicon layer formed into the ledge.

摘要翻译： 一种用于形成集成电路内使用的层叠容器电容器的方法。 连续形成在半导体衬底上的是第一电介质层，第二电介质层和图案化掩模层。 在各向同性蚀刻工艺中，第一介电层比第二介电层慢。 通过使用图案化掩模层作为掩模的各向异性蚀刻工艺，至少部分地蚀刻孔，穿过第一介电层。 通过使用图案化掩模层作为掩模的各向同性蚀刻工艺，蚀刻第二介电层以产生形成在第一介电层上方并在图案化掩模层下方的凸缘。 然后去除图案化的掩模层。 然后形成各向异性和各向异性蚀刻的孔径是第一多晶硅层，第三介电层和第二多晶硅层。 最后，填充的各向同性蚀刻的孔被平坦化，直到暴露出形成在凸缘中的第一多晶硅层的凸缘。

公开(公告)号：US5602053A

公开(公告)日：1997-02-11

申请号：US628068

申请日：1996-04-08

申请人： Jiazhen Zheng ,  Lap Chan

发明人： Jiazhen Zheng ,  Lap Chan

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L21/70

CPC分类号： H01L23/5252 ,  H01L21/76807 ,  H01L21/76888 ,  H01L2924/0002

摘要： An improved antifuse design has been achieved by providing a structure includes a pair of alternating layers of silicon nitride and amorphous silicon sandwiched between two dual damascene connectors. Said structure provides the advantage, over the prior art, that all electrically active surfaces of the fuse structure are planar, so no potential failure spots resulting from surface unevenness can be formed. A process for manufacturing said fuse structure is also provided and involves fewer masking steps than related structures of the prior art.

摘要翻译： 通过提供包括夹在两个双镶嵌连接器之间的一对氮化硅交换层和非晶硅的结构已经实现了改进的反熔丝设计。 与现有技术相比，所述结构提供了熔丝结构的所有电活性表面是平面的优点，因此不会形成由表面凹凸产生的潜在故障点。 还提供了用于制造所述熔丝结构的工艺，并且涉及比现有技术的相关结构更少的掩模步骤。

公开(公告)号：US20130317907A1

公开(公告)日：2013-11-28

申请号：US13480262

申请日：2012-05-24

申请人： Bin Duan ,  Lap Chan

发明人： Bin Duan ,  Lap Chan

IPC分类号： G06Q30/02

CPC分类号： G06Q30/02

摘要： Disclosed is a process for marketing a product that is triggered by the user. When a user browses a product on a seller's web site, the user may be presented with a product tracking mechanism. The user may trigger product tracking, including specifying kinds of product notifications on the product and how those notifications are received.

摘要翻译： 公开了一种由用户触发的产品的营销过程。 当用户浏览卖方网站上的产品时，可能会向用户显示产品跟踪机制。 用户可以触发产品跟踪，包括指定产品上的产品通知类型以及这些通知的接收方式。

公开(公告)号：US08354321B2

公开(公告)日：2013-01-15

申请号：US13277197

申请日：2011-10-19

申请人： Benjamin Colombeau ,  Sai Hooi Yeong ,  Francis Benistant ,  Bangun Indajang ,  Lap Chan

发明人： Benjamin Colombeau ,  Sai Hooi Yeong ,  Francis Benistant ,  Bangun Indajang ,  Lap Chan

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L29/78612 ,  H01L29/66537 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

摘要： A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

摘要翻译： 一种晶体管，其包括设置在与栅极的相对侧相邻的衬底中的晕圈。 晕区具有上部和下部区域。 上部区域是具有多余空位的结晶区域，下部区域是非晶区域。 源极/漏极扩散区域设置在光晕区域中。 源极/漏极扩散区域与上部和下部晕圈重叠。 该架构提供最小的延伸电阻以及最小的横向扩散，以实现更好的CMOS器件缩放。

公开(公告)号：US08242872B2

公开(公告)日：2012-08-14

申请号：US11779892

申请日：2007-07-19

申请人： Chee Chong Lim ,  Kok Wai Chew ,  Kiat Seng Yeo ,  Suh Fei Lim ,  Manh Anh Do ,  Lap Chan

发明人： Chee Chong Lim ,  Kok Wai Chew ,  Kiat Seng Yeo ,  Suh Fei Lim ,  Manh Anh Do ,  Lap Chan

IPC分类号： H01F5/00 ,  H01F27/28

CPC分类号： H01F27/2804 ,  H01F17/0013 ,  H01F27/006 ,  H01F2017/0073 ,  H01L2924/3011 ,  Y10T29/4902

摘要： Embodiments of the invention provide a transformer comprising: a first coil element having a transverse axis along a transverse direction, the first coil element having p turns where p is greater than or equal to 1; and a second coil element having a transverse axis generally parallel to the transverse axis of the first coil element, the second coil element having n turns, where n is greater than or equal to 5p; wherein the first and second coil elements are arranged to provide electromagnetic coupling between the coil elements along a portion of a length of the second coil element in both a transverse direction parallel to the transverse axes and a lateral direction, wherein the lateral direction is a direction normal to the transverse axes.

摘要翻译： 本发明的实施例提供了一种变压器，包括：第一线圈元件，其沿着横向具有横向轴线，所述第一线圈元件具有p匝，其中p大于或等于1; 以及第二线圈元件，其具有大致平行于所述第一线圈元件的横向轴线的横轴，所述第二线圈元件具有n匝，其中n大于或等于5p; 其中所述第一和第二线圈元件布置成沿平行于横向轴线的横向方向和横向方向沿着所述第二线圈元件的长度的一部分在所述线圈元件之间提供电磁耦合，其中所述横向方向是 垂直于横轴。