公开(公告)号：US20210263847A1

公开(公告)日：2021-08-26

申请号：US16800356

申请日：2020-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： James S. Rehmeyer ,  Libo Wang ,  Anthony D. Veches ,  Debra M. Bell ,  Di Wu

IPC: G06F12/06 ,  G06F11/10 ,  G06F16/2455

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data may be retrieved from a memory array for the pattern matching operation by a read operation, a refresh operation, an error correction operation, and/or a pattern matching operation. The data may be retrieved from incoming data input lines instead of or in addition to the memory array. How the data is stored or retrieved for pattern matching operations may be controlled by a memory controller.

公开(公告)号：US20210225431A1

公开(公告)日：2021-07-22

申请号：US17226975

申请日：2021-04-09

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Nathaniel J. Meier ,  Joo-Sang Lee

IPC: G11C11/406 ,  H01L25/065

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of skipped refresh operations on a memory. Memory cells of memories may need to periodically perform refresh operations. In some instances, auto-refresh operations may be periodically skipped when charge retention characteristics of the memory cells of the memory exceed the auto-refresh frequency. To reduce peak current draw during refresh operations, the skipped refresh operations may be staggered across different portions of the memory. In one example, the skipped refresh operation may be staggered in time among memory dies of the memory to limit a number of memory dies that are performing an auto-refresh operation to a maximum number. In another example, the skipped refresh operation may be staggered in time among memory banks of a single memory array to limit a number of memory banks that are performing an auto-refresh operation to a maximum number.

公开(公告)号：US20210082529A1

公开(公告)日：2021-03-18

申请号：US17107235

申请日：2020-11-30

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  George B. Raad ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C16/34 ,  G11C11/406

Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.

公开(公告)号：US20210065796A1

公开(公告)日：2021-03-04

申请号：US16553821

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Debra M. Bell ,  James S. Rehmeyer ,  Robert Bunnell ,  Nathaniel J. Meier

IPC: G11C14/00 ,  G11C17/18 ,  G11C17/16 ,  G11C11/4096 ,  G11C11/4072

Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells and a fuse array configured to store precondition data. The precondition data can identify a portion of the memory array, specify a predetermined precondition state, or a combination thereof. When the memory device powers on, the memory device can be configured to automatically retrieve the precondition data from the fuse array and/or to write memory cells in the portion of the memory array to the predetermined precondition state before executing an access command.

公开(公告)号：US10885967B2

公开(公告)日：2021-01-05

申请号：US16247277

申请日：2019-01-14

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Debra M. Bell ,  George B. Raad ,  Brian P. Callaway ,  Joshua E. Alzheimer

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/403

Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.

公开(公告)号：US10825505B2

公开(公告)日：2020-11-03

申请号：US16818981

申请日：2020-03-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： James S. Rehmeyer

IPC: G11C11/406 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/408

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations. Memory dies may need to periodically perform refresh operations, which may be auto-refresh operations or targeted refresh operations. Targeted refresh operations may draw less current than auto-refresh operations. When dies are collected into a group (e.g., a memory stack, a memory module) the timing of targeted refresh operations may be staggered between the different dies to help reduce the peak current drawn. The targeted refresh operations may be staggered such that, when a maximum number of the dies are performing a refresh operation, at least one of the dies performs a targeted refresh operation instead of an auto-refresh operation.

公开(公告)号：US10762946B2

公开(公告)日：2020-09-01

申请号：US16237013

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/406 ,  G11C11/4074 ,  G11C16/10 ,  G11C11/4072

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a plurality of memory cells arranged in a plurality of memory regions and (ii) inhibit circuitry. In some embodiments, the inhibit circuitry is configured to disable one or more memory regions of the plurality of memory regions from receiving refresh commands such that memory cells of the one or more memory regions are not refreshed during refresh operations of the memory device. In these and other embodiments, the memory controller is configured to track memory regions that include utilized memory cells and/or to write data to the memory regions in accordance with a programming sequence of the memory device.

公开(公告)号：US20200273518A1

公开(公告)日：2020-08-27

申请号：US15930268

申请日：2020-05-12

Applicant: Micron Technology, Inc.

Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C11/406 ,  G11C11/00 ,  G11C13/00 ,  G11C11/22 ,  G11C11/16

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

公开(公告)号：US10748600B2

公开(公告)日：2020-08-18

申请号：US16216894

申请日：2018-12-11

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  George B. Raad ,  Debra M. Bell ,  Markus H. Geiger ,  Anthony D. Veches

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/406

Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

公开(公告)号：US20200219555A1

公开(公告)日：2020-07-09

申请号：US16818981

申请日：2020-03-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： James S. Rehmeyer

IPC: G11C11/406 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4076

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations. Memory dies may need to periodically perform refresh operations, which may be auto-refresh operations or targeted refresh operations. Targeted refresh operations may draw less current than auto-refresh operations. When dies are collected into a group (e.g., a memory stack, a memory module) the timing of targeted refresh operations may be staggered between the different dies to help reduce the peak current drawn. The targeted refresh operations may be staggered such that, when a maximum number of the dies are performing a refresh operation, at least one of the dies performs a targeted refresh operation instead of an auto-refresh operation.