公开(公告)号：US10896713B2

公开(公告)日：2021-01-19

申请号：US16695848

申请日：2019-11-26

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.

公开(公告)号：US10855295B2

公开(公告)日：2020-12-01

申请号：US16859786

申请日：2020-04-27

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Daniele Vimercati ,  Jahanshir Javanifard

IPC: H03L7/181 ,  H03L7/193 ,  H03L7/099 ,  H03K5/13 ,  H03L7/08 ,  H03K21/10

Abstract: Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

公开(公告)号：US20200335152A1

公开(公告)日：2020-10-22

申请号：US16871495

申请日：2020-05-11

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/22

Abstract: Methods, systems, and devices for operating a memory device are described. A sense amplifier may be used to precharge an access line to increase the reliability of the sensing operation. The access line may then charge share with the memory cell and a capacitor, which may be a reference capacitor, which may result in high-level states and low-level states on the access line. By precharging the access line with the sense amplifier and implementing charge sharing between the access line and a capacitor, the resulting high-level state and the low-level states on the access line may account for any offset voltage associated with the sense amplifier.

公开(公告)号：US20200259497A1

公开(公告)日：2020-08-13

申请号：US16859786

申请日：2020-04-27

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Daniele Vimercati ,  Jahanshir Javanifard

IPC: H03L7/193 ,  H03L7/099 ,  H03K21/10 ,  H03L7/08 ,  H03K5/13

Abstract: Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

公开(公告)号：US20200152243A1

公开(公告)日：2020-05-14

申请号：US16746613

申请日：2020-01-17

Applicant: Micron Technology, Inc.

Inventor： Mahdi Jamali ,  William A. Melton ,  Daniele Vimercati ,  Xinwei Guo ,  Yasuko Hattori

IPC: G11C7/06 ,  G11C11/22 ,  G11C11/4091 ,  G11C7/08

Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.

公开(公告)号：US10600467B2

公开(公告)日：2020-03-24

申请号：US16536050

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22 ,  G11C7/06

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. For example, a switching component connected to a digit line may also be connected to an offset capacitor selected to compensate for a threshold voltage offset. The offset capacitor may be discharged in conjunction with a read operation, resulting in a threshold voltage applied to the switching component. This may enable all or substantially all of the stored charge of the ferroelectric memory cell to be extracted and transferred to a sense capacitor through the transistor. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.

公开(公告)号：US10573355B2

公开(公告)日：2020-02-25

申请号：US16512963

申请日：2019-07-16

Applicant: Micron Technology, Inc.

Inventor： Mahdi Jamali ,  William A. Melton ,  Daniele Vimercati ,  Xinwei Guo ,  Yasuko Hattori

IPC: G11C7/06

Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.

公开(公告)号：US20200005851A1

公开(公告)日：2020-01-02

申请号：US16504876

申请日：2019-07-08

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo ,  Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.

公开(公告)号：US20190189178A1

公开(公告)日：2019-06-20

申请号：US15846765

申请日：2017-12-19

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22 ,  G11C11/56 ,  G11C13/00

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/2297 ,  G11C11/5657 ,  G11C13/004

Abstract: The present disclosure includes apparatuses, methods, and systems for current separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell having a ferroelectric material, and determining a data state of the memory cell by separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell and a second current output by the memory cell while the sensing voltage is being applied to the memory cell, wherein the first current output by the memory cell corresponds to a first polarization state of the ferroelectric material of the memory cell and the second current output by the memory cell corresponds a second polarization state of the ferroelectric material of the memory cell.

公开(公告)号：US20190147933A1

公开(公告)日：2019-05-16

申请号：US16184823

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further include a first capacitor coupled to the first transistor and a second capacitor coupled to the second transistor and a first switching component coupled between a voltage source and the first capacitor and the second capacitor. For example, the first switching component may be activated, a reference voltage may be applied to the sense component, and the first switching component may then be deactivated. In some examples, a voltage offset may be measured across both the first and the second capacitor.