公开(公告)号：US20250068345A1

公开(公告)日：2025-02-27

申请号：US18743783

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yuan He ,  Kang-Yong Kim ,  Randall J. Rooney ,  Dong Pan

IPC: G06F3/06

Abstract: Apparatuses and methods per-row count based refresh target identification. A memory device stores count values associated with the word lines. An aggressor detector circuit stores a maximum of the count values and a row address associated with the maximum count value. Responsive to a targeted refresh signal, the stored count value is compared to a threshold. If the count value has crossed the threshold, then a targeted refresh operation may be performed on one or more refresh addresses based on the stored address, and the count value may be reset.

公开(公告)号：US20240386941A1

公开(公告)日：2024-11-21

申请号：US18425149

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Dong Pan ,  Scott D. Van De Graaff

IPC: G11C11/4093 ,  G11C29/50 ,  G11C11/4076

Abstract: Systems and methods described herein may increase voltages sensed during testing of a device-under-test, which may increase an ease of sensing by a comparator, where a relatively less sensitive comparator may be used to detect the increased voltage sensed. Indeed, first readout circuitry may include two or more diodes coupled in series to a first resistor, which may help increase the voltages sensed via the first readout circuitry.

公开(公告)号：US20240363191A1

公开(公告)日：2024-10-31

申请号：US18634096

申请日：2024-04-12

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yuan He ,  Kang-Yong Kim ,  Dong Pan

IPC: G11C29/00

CPC classification number: G11C29/76 ,  G11C29/789

Abstract: Apparatuses and techniques for implementing usage-based disturbance (UBD) counter repair are described. In example implementations, a memory device includes multiple memory rows, multiple corresponding UBD counters, a register, and a spare UBD counter. If a UBD counter is faulty, logic can substitute the spare UBD counter. To do so, the logic can store a row address corresponding to the faulty UBD counter in the register. The logic can increment a value in the spare UBD counter responsive to a row activation corresponding to the stored row address. A mitigation procedure on a row that may be affected by the activation can be performed based on the value. A host device can control, at least partially, the UBD counter repair process. In these manners, a repair of a faulty UBD counter can be accomplished faster and/or with fewer resources as compared to replacing a memory row and corresponding UBD counter.

公开(公告)号：US20240038321A1

公开(公告)日：2024-02-01

申请号：US17873869

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Subhasis Sasmal ,  Dong Pan

IPC: G11C29/50 ,  G11C29/12 ,  G01R19/165

CPC classification number: G11C29/50004 ,  G11C29/12005 ,  G01R19/16528 ,  G01R19/16533 ,  G11C2029/5004

Abstract: An electronic device, such as a memory device, may include various circuit components. The electronic device may also include one or more voltage testing circuits to determine whether signals of one or more of the circuit components are within acceptable voltage ranges of the respective circuit components. Systems and methods are described to improve correct voltage measurement of the received signals by a voltage testing circuit. In particular, multiple supply voltage levels are provided to different components of the voltage testing circuit to provide a sufficient headroom voltage gap between received signals and the supply voltages. For example, some active circuits (e.g., operational amplifiers) of the voltage testing circuit may receive a higher supply voltage of the electronic device compared to one or more other circuits of the voltage testing circuit.

公开(公告)号：US20220415427A1

公开(公告)日：2022-12-29

申请号：US17822033

申请日：2022-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dong Pan

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/406 ,  G11C7/06 ,  G11C29/20

Abstract: Counters may be provided for individual word lines of a memory for tracking word line accesses. In some examples, multiple counters may be provided for individual word lines. In some examples, the counters may be included on the word lines. The counters may be incremented responsive to word line accesses in some examples. In some examples, the counters may be incremented responsive for a time period for which a word line is held open. In some examples, the counters may be incremented responsive to both word line accesses and time periods for which the word line is held open. In some examples, count values for the counters may be written back to the counters after incrementing. In some examples, the count values may be written back prior to receiving a precharge command.

公开(公告)号：US20220352882A1

公开(公告)日：2022-11-03

申请号：US17813291

申请日：2022-07-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhiqi Huang ,  Weilu Chu ,  Dong Pan

IPC: H03K5/134 ,  G11C11/4076 ,  G11C11/4093

Abstract: Methods and apparatuses are provided for temperature independent resistive-capacitive delay circuits of a semiconductor device. For example, delays associated with ZQ calibration or timing of the RAS chain may be implemented that to include circuitry that exhibits both proportional to absolute temperature (PTAT) characteristics and complementary to absolute temperature (CTAT) characteristics in order to control delay times across a range of operating temperatures. The RC delay circuits may include a first type of circuitry having impedance with PTAT characteristics that is coupled to an output node in parallel with a second type of circuitry having impedance with CTAT characteristics. The first type of circuitry may include a resistor and the second type of circuitry may include a transistor, in some embodiments.

公开(公告)号：US20220270670A1

公开(公告)日：2022-08-25

申请号：US17662733

申请日：2022-05-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Wu ,  Yu Zhang ,  Dong Pan

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/402

Abstract: Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.

公开(公告)号：US11380370B2

公开(公告)日：2022-07-05

申请号：US16646503

申请日：2017-09-22

Applicant: Micron Technology, Inc.

Inventor： Jun Wu ,  Dong Pan

IPC: G11C5/14 ,  G11C11/4074 ,  G11C16/30 ,  H02M3/07

Abstract: Apparatus and methods that have a semiconductor charge pump can be implemented in a variety of applications. Such a charge pump can have a charge pump unit core that includes a pump section and a single passgate coupled to the pump section to transfer charge, where the single passgate is a n-channel metal-oxide semiconductor (NMOS) transistor coupled directly to an input and an output of the charge pump unit core. The transfer of charge can be based on a set of clock signals. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US11335396B1

公开(公告)日：2022-05-17

申请号：US16952804

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

IPC: G11C11/4076 ,  G11C7/22 ,  G11C11/22

Abstract: Methods, systems, and devices for timing signal delay for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. A memory device may include delay components having a configurable impedance based at least in part on one or more fabrication characteristics of the memory device, one or more operating conditions of the memory device, one or more bias voltages, or a combination thereof.

公开(公告)号：US11227650B1

公开(公告)日：2022-01-18

申请号：US17002398

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

IPC: G11C8/18 ,  G11C11/4076

Abstract: An electronic device includes a first input that receives an input signal when the electronic device is in operation, a long L gate comprising a long L transistor, a first activation transistor coupled to a gate of the long L transistor, and a second activation transistor coupled to the gate of the long L transistor. The electronic device also includes a switch directly coupled to a second input of the long L gate, a path directly coupled to a first output of the long L gate, a capacitor coupled to the path, and a second output that when in operation transmits an output signal as a delayed signal with respect to the input signal.