公开(公告)号：US20210342090A1

公开(公告)日：2021-11-04

申请号：US16865163

申请日：2020-05-01

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Marco Sforzin ,  Paolo Amato

IPC: G06F3/06

Abstract: Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.

公开(公告)号：US20210165577A1

公开(公告)日：2021-06-03

申请号：US17175155

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Innocenzo Tortorelli

IPC: G06F3/06 ,  G11C7/08 ,  G11C7/22 ,  G11C8/12 ,  G11C13/00 ,  G11C16/34

Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array of memory cells and a second signal to a second portion of the array of memory cells.

公开(公告)号：US20210090648A1

公开(公告)日：2021-03-25

申请号：US17110782

申请日：2020-12-03

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato

IPC: G11C13/00

Abstract: Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.

公开(公告)号：US20210057015A1

公开(公告)日：2021-02-25

申请号：US16544730

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato

IPC: G11C11/4074 ,  G11C11/409 ,  G06F12/14

Abstract: Methods, systems, and devices for distribution-following access operations for a memory device are described. In an example, the described techniques may include identifying an activation of a first memory cell at a first condition of a biasing operation, and identifying an activation of a second memory cell at a second condition of the biasing operation, and determining a parameter of an access operation based at least in part on a difference between the first condition and the second condition. In some examples, the memory cells may be associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time.

公开(公告)号：US10921989B2

公开(公告)日：2021-02-16

申请号：US15683821

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Innocenzo Tortorelli

IPC: G11C16/16 ,  G06F3/06 ,  G11C7/22 ,  G11C16/34 ,  G11C7/08 ,  G11C13/00 ,  G11C8/12

Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array of memory cells and a second signal to a second portion of the array of memory cells.

公开(公告)号：US10796755B2

公开(公告)日：2020-10-06

申请号：US15957098

申请日：2018-04-19

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin

IPC: G11C16/28 ,  G11C11/56 ,  G11C13/00 ,  G11C16/04 ,  G11C11/16

Abstract: Permutation coding for improved memory cell operations are described. An example apparatus can include an array of memory cells each programmable to a plurality of states. A controller coupled to the array is configured to determine an encoded data pattern stored by a number of groups of memory cells. Each of the number of groups comprises a set of memory cells programmed to one of a plurality of different collective state permutations each corresponding to a permutation in which the cells of the set are each programmed to a different one of the plurality of states to which they are programmable. The controller is configured to determine the encoded data pattern by, for each of the number of groups, determining the one of the plurality of different collective state permutations to which the respective set is programmed by direct comparison of threshold voltages of the cells of the set.

公开(公告)号：US10754725B2

公开(公告)日：2020-08-25

申请号：US16229578

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin

IPC: G06F11/10 ,  G06F3/06 ,  G06F9/00 ,  G06F11/00

Abstract: Methods and apparatus for Exclusive OR (XOR) programming of a memory device are described. A program internal to a device calculates parity or other values using an XOR Program Rule. In some embodiments, the program generates and stores a parity result directly in the memory device itself without intervention by an external controller. A method of parity generation in a memory device comprises executing an internal self-accumulating parity program, wherein the program accumulates a parity sum by superimposing newly accumulated parity information over previously stored parity information in the auxiliary memory system. In a stand-alone device embodiment, a new command “XOR program” is received with address and input data parameters causing stored data to be read at the input address and an XOR operation of the read data and new input data is performed. The results of the computation are written into memory.

公开(公告)号：US10714185B2

公开(公告)日：2020-07-14

申请号：US16168952

申请日：2018-10-24

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Umberto Di Vincenzo

IPC: G11C11/34 ,  G11C16/12 ,  G11C16/28 ,  G11C7/14 ,  G11C11/24 ,  G11C7/06 ,  G11C11/404 ,  G11C13/00 ,  G11C11/56

Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

公开(公告)号：US20200135276A1

公开(公告)日：2020-04-30

申请号：US16168952

申请日：2018-10-24

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Umberto Di Vincenzo

IPC: G11C16/12 ,  G11C16/28 ,  G11C11/404 ,  G11C11/24 ,  G11C7/06 ,  G11C7/14

Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

公开(公告)号：US10606694B2

公开(公告)日：2020-03-31

申请号：US15958496

申请日：2018-04-20

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/29 ,  H03M13/11

Abstract: Apparatuses and methods related to correcting errors can include using fast decoding (FD) decoders and accurate decoding (AD) decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.