公开(公告)号：US20200066327A1

公开(公告)日：2020-02-27

申请号：US16110349

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/4097 ,  H01L27/108 ,  H01L27/12 ,  G11C11/4091

Abstract: In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.

公开(公告)号：US20200051608A1

公开(公告)日：2020-02-13

申请号：US16523653

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Tae H. Kim ,  Charles L. Ingalls

IPC: G11C11/4074 ,  G11C11/408 ,  G11C11/4091

Abstract: A memory device is provided. The memory device includes a memory array having at least one memory cell. The memory device further includes a sense amplifier circuit configured to read data from the at least one memory cell, write data to the at least one memory cell, or a combination thereof. The memory device additionally includes a first bus configured to provide a first electric power to the sense amplifier circuit, and a second bus configured to provide a second electric power to a second circuit, wherein the first bus and the second bus are configured to be electrically coupled to each other to provide for the first electric power and the second electric power to the at least one memory cell.

公开(公告)号：US10431282B2

公开(公告)日：2019-10-01

申请号：US16035135

申请日：2018-07-13

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US20190279984A1

公开(公告)日：2019-09-12

申请号：US16418150

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore ,  Charles L. Ingalls ,  Steve V. Cole

IPC: H01L27/108 ,  G11C11/4097 ,  H01L49/02 ,  G11C11/4094 ,  G11C5/02 ,  H01L29/08 ,  G11C11/408 ,  G11C11/403

Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

公开(公告)号：US10347635B2

公开(公告)日：2019-07-09

申请号：US15986628

申请日：2018-05-22

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore ,  Charles L. Ingalls ,  Steve V. Cole

IPC: H01L27/108 ,  G11C11/408 ,  H01L49/02 ,  G11C11/4097 ,  H01L29/08 ,  G11C11/4094 ,  G11C5/02 ,  G11C11/403 ,  G11C11/4091

Abstract: Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

公开(公告)号：US20190088653A1

公开(公告)日：2019-03-21

申请号：US16183528

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore

IPC: H01L27/108 ,  G11C11/403 ,  H01L29/78 ,  H01L49/02 ,  H01L27/07 ,  H01L29/10 ,  G11C7/18 ,  H01L23/528 ,  H01L29/08

Abstract: Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells.

公开(公告)号：US10157926B2

公开(公告)日：2018-12-18

申请号：US15664161

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  H01L29/78 ,  G11C11/403 ,  H01L23/528 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US20180358084A1

公开(公告)日：2018-12-13

申请号：US16105889

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  HUY T. VO ,  PATRICK MULLARKEY ,  JEFFREY P. WRIGHT ,  MICHAEL A. SHORE

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/406 ,  G11C11/4072

Abstract: Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.

公开(公告)号：US20180358083A1

公开(公告)日：2018-12-13

申请号：US16105631

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/4091 ,  H01L27/108 ,  G11C11/4097 ,  G11C11/4094 ,  G11C11/403 ,  G11C7/06 ,  G11C5/02 ,  G11C7/18 ,  G11C11/4096 ,  G11C8/16

Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.

公开(公告)号：US20180061834A1

公开(公告)日：2018-03-01

申请号：US15664143

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Michael Amiel Shore

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/07 ,  H01L29/78

CPC classification number: H01L27/108 ,  G11C7/18 ,  G11C11/403 ,  H01L23/528 ,  H01L27/07 ,  H01L28/60 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/7827

Abstract: Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells.