公开(公告)号：US20120244640A1

公开(公告)日：2012-09-27

申请号：US13226960

申请日：2011-09-07

申请人： Yuichi OHSAWA ,  Shigeki Takahashi ,  Junichi Ito ,  Daisuke Saida ,  Kyoichi Suguro ,  Hiroaki Yoda

发明人： Yuichi OHSAWA ,  Shigeki Takahashi ,  Junichi Ito ,  Daisuke Saida ,  Kyoichi Suguro ,  Hiroaki Yoda

IPC分类号： H01L43/12

CPC分类号： H01L43/12 ,  H01L29/82

摘要： According to one embodiment, a method of manufacturing a multilayer film, the method includes forming a first layer, forming a second layer on the first layer, and transcribing a crystal information of one of the first and second layers to the other one of the first and second layers by executing a GCIB-irradiation to the second layer.

摘要翻译： 根据一个实施例，一种制造多层膜的方法，该方法包括：形成第一层，在第一层上形成第二层，以及将第一层和第二层之一的晶体信息转录到第一层中的另一层 并且通过对第二层执行GCIB照射来产生第二层。

公开(公告)号：US20110294291A1

公开(公告)日：2011-12-01

申请号：US13035546

申请日：2011-02-25

申请人： Yukiteru Matsui ,  Gaku Minamihaba ,  Hajime Eda ,  Masayoshi Iwayama ,  Minoru Amano ,  Masatoshi Yoshikawa ,  Motoyuki Sato ,  Kyoichi Suguro ,  Masako Kodera

发明人： Yukiteru Matsui ,  Gaku Minamihaba ,  Hajime Eda ,  Masayoshi Iwayama ,  Minoru Amano ,  Masatoshi Yoshikawa ,  Motoyuki Sato ,  Kyoichi Suguro ,  Masako Kodera

IPC分类号： H01L21/768

CPC分类号： H01L21/02697 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76883 ,  H01L27/228

摘要： According to one embodiment, a semiconductor device includes a switch element provided in a surface area of a semiconductor substrate, a contact plug with an upper surface and a lower surface, and a function element provided on the upper surface of the contact plug. The lower surface of the contact plug is connected to the switch element. The upper surface of the contact plug has a maximum roughness of 0.2 nm or less.

摘要翻译： 根据一个实施例，半导体器件包括设置在半导体衬底的表面区域中的开关元件，具有上表面和下表面的接触插塞以及设置在接触插塞的上表面上的功能元件。 接触插头的下表面连接到开关元件。 接触塞的上表面的最大粗糙度为0.2nm以下。

公开(公告)号：US07781848B2

公开(公告)日：2010-08-24

申请号：US11704924

申请日：2007-02-12

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

IPC分类号： H01L29/78

CPC分类号： H01L21/823857 ,  H01L21/823814 ,  H01L21/823842

摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

摘要翻译： 半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。 源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。 第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。 第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。 第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。 栅电极形成在第二栅绝缘膜上。

公开(公告)号：US20100193874A1

公开(公告)日：2010-08-05

申请号：US12757658

申请日：2010-04-09

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

IPC分类号： H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/823814 ,  H01L21/823842

摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

摘要翻译： 半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。 源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。 第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。 第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。 第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。 栅电极形成在第二栅绝缘膜上。

公开(公告)号：US07579231B2

公开(公告)日：2009-08-25

申请号：US10815932

申请日：2004-04-02

申请人： Kouji Matsuo ,  Tomohiro Saito ,  Kyoichi Suguro ,  Shinichi Nakamura

发明人： Kouji Matsuo ,  Tomohiro Saito ,  Kyoichi Suguro ,  Shinichi Nakamura

IPC分类号： H01L21/8238 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/62

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/31683 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66181 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

摘要： Disclosed is a method of manufacturing a semiconductor device, comprising forming a metal compound film directly or indirectly on a semiconductor substrate, forming a metal-containing insulating film consisting of a metal oxide film or a metal silicate film by oxidizing the metal compound film, and forming an electrode on the metal-containing insulating film.

摘要翻译： 公开了一种制造半导体器件的方法，包括在半导体衬底上直接或间接形成金属化合物膜，通过氧化金属化合物膜形成由金属氧化物膜或金属硅酸盐膜构成的含金属的绝缘膜，以及 在含金属的绝缘膜上形成电极。

公开(公告)号：US20090139449A1

公开(公告)日：2009-06-04

申请号：US12289895

申请日：2008-11-06

申请人： Kyoichi Suguro ,  Takeshi Shibata ,  Kazuyoshi Sugihara ,  Kouji Matsuo

发明人： Kyoichi Suguro ,  Takeshi Shibata ,  Kazuyoshi Sugihara ,  Kouji Matsuo

IPC分类号： B05C11/00

CPC分类号： B82Y10/00 ,  C23C14/042 ,  C23C14/48 ,  G03F1/20 ,  H01J2237/0453 ,  H01J2237/31788 ,  H01L21/266 ,  Y10T428/24273

摘要： Preparing a stencil mask comprising a silicon thin film in which an opening for selectively irradiating charged particles to a semiconductor substrate is provided and whose irradiation surface on which the charged particles are irradiated is implanted with an impurity, and selectively irradiating charged particles to the semiconductor substrate using the stencil mask which is opposingly arranged on the semiconductor substrate.

摘要翻译： 制备包括硅薄膜的模板掩模，其中用于选择性地将带电粒子照射到半导体基板的开口，并且其上照射有带电粒子的照射面被注入杂质，并且将带电粒子选择性地照射到半导体衬底 使用相对设置在半导体衬底上的模板掩模。

公开(公告)号：US07501332B2

公开(公告)日：2009-03-10

申请号：US11097259

申请日：2005-04-04

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/425

CPC分类号： H01L21/2236 ,  H01L21/823814 ,  Y10S438/918 ,  Y10S438/964

摘要： A doping method includes implanting first impurity ions into a semiconductor substrate, so as to form a damaged region in the vicinity of a surface of the semiconductor substrate, the first impurity ions not contributing to electric conductivity; implanting second impurity ions into the semiconductor substrate through the damaged region, the second impurity ions having an atomic weight larger than the first impurity ions and contributing to the electric conductivity; and heating the surface of the semiconductor substrate with a light having a pulse width of about 0.1 ms to about 100 ms, so as to activate the second impurity ions.

摘要翻译： 掺杂方法包括将第一杂质离子注入到半导体衬底中，以在半导体衬底的表面附近形成损伤区域，不对导电性有贡献的第一杂质离子; 通过损伤区域将第二杂质离子注入到半导体衬底中，第二杂质离子的原子量大于第一杂质离子并有助于导电性; 并用脉冲宽度为约0.1ms至约100ms的光来加热半导体衬底的表面，以激活第二杂质离子。

公开(公告)号：US20080157214A1

公开(公告)日：2008-07-03

申请号：US12071887

申请日：2008-02-27

申请人： Kazuaki Nakajima ,  Kyoichi Suguro

发明人： Kazuaki Nakajima ,  Kyoichi Suguro

IPC分类号： H01L27/092

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092

摘要： A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the insulation film, a first metal silicide layer formed on the bottom of the first contact hole, the first metal silicide layer being provided by a reaction of the n-channel impurity diffused region of the n-channel MISFET with a first metal, a second contact hole formed in the insulation film, a second metal silicide layer formed on the bottom of the second contact hole, the second metal silicide layer being provided by a reaction of the p-channel impurity diffused region of the p-channel MISFET with a second metal, and a work function of the second metal silicide layer being higher than that of the first metal silicide layer.

摘要翻译： 公开了一种半导体器件，其包括硅衬底，互补MISFET电路，形成在硅衬底上的绝缘膜，形成在绝缘膜中的第一接触孔，形成在第一接触孔的底部上的第一金属硅化物层 通过n沟道MISFET的n沟道杂质扩散区域与第一金属的反应提供第一金属硅化物层，形成在绝缘膜中的第二接触孔，形成在第二金属硅化物层的底部的第二金属硅化物层 所述第二接触孔，所述第二金属硅化物层由所述p沟道MISFET的p沟道杂质扩散区域与第二金属的反应提供，并且所述第二金属硅化物层的功函数高于所述第二金属硅化物层的功函数 第一金属硅化物层。

公开(公告)号：US07339247B2

公开(公告)日：2008-03-04

申请号：US11488849

申请日：2006-07-19

申请人： Takeshi Shibata ,  Hisanori Misawa ,  Kyoichi Suguro

发明人： Takeshi Shibata ,  Hisanori Misawa ,  Kyoichi Suguro

IPC分类号： H01L31/0232

CPC分类号： H01L21/266

摘要： A method of manufacturing a semiconductor device is disclosed, which comprises setting a stencil mask above a substrate to be processed in confronting to the substrate, the stencil mask having an opening, and irradiating the substrate with charged particles through the opening of the stencil mask, while adjusting a potential difference between the stencil mask and the substrate depending on a value of a current flowing between the substrate and the stencil mask.

摘要翻译： 公开了一种制造半导体器件的方法，其包括将待加工衬底上的模版掩模设置在与衬底相对的位置上，所述模板掩模具有开口，并且通过所述模板掩模的开口对所述衬底照射带电粒子， 同时根据在基板和模板掩模之间流动的电流的值调节模板掩模和基板之间的电位差。

公开(公告)号：US07267927B2

公开(公告)日：2007-09-11

申请号：US10743290

申请日：2003-12-23

申请人： Takeshi Shibata ,  Kyoichi Suguro

发明人： Takeshi Shibata ,  Kyoichi Suguro

IPC分类号： G03C5/00

CPC分类号： G03F1/20 ,  G03F7/70066 ,  G03F7/70983 ,  H01J2237/31794 ,  Y10S430/143

摘要： A method for fabricating a semiconductor device and an equipment for fabricating the semiconductor device are described.According to the method and the equipment, a semiconductor substrate is irradiated with a particle beam through an opening formed in a thin film portion of a stencil mask having the thin film portion and a supporting portion supporting the thin film portion. The method and the equipment are controlled so that the supporting portion of the stencil mask can be irradiated with the fringe of the particle beam. As a result, the method and the equipment provide suppressing deterioration such as deformation or breakage of the stencil mask.

摘要翻译： 对半导体装置的制造方法及半导体装置的制造装置进行说明。 根据该方法和设备，通过形成在具有薄膜部分的模板掩模的薄膜部分中的开口和支撑薄膜部分的支撑部分，通过粒子束照射半导体衬底。 控制该方法和设备，使得模板掩模的支撑部分可以用粒子束的边缘照射。 结果，该方法和设备抑制了模板掩模的变形或断裂等劣化。