公开(公告)号：US20220059410A1

公开(公告)日：2022-02-24

申请号：US17516404

申请日：2021-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L21/8234 ,  H01L23/535 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

公开(公告)号：US11251090B2

公开(公告)日：2022-02-15

申请号：US16737591

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Wang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Kuo-Cheng Chiang ,  Chih-Chao Chou ,  Pei-Hsun Wang

IPC: H01L21/8238 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L21/306 ,  H01L21/311 ,  H01L21/027 ,  H01L21/762 ,  H01L29/66

Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

公开(公告)号：US11245029B2

公开(公告)日：2022-02-08

申请号：US16548483

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wang-Chun Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78

Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a semiconductor stack having first sacrificial layers and first semiconductor layers laid out alternately. The method also includes patterning the semiconductor stack to form a first fin structure and a second fin structure. The method further includes replacing the second fin structure with a third fin structure having second sacrificial layers and second semiconductor layers laid out alternately. In addition, the method includes removing the first sacrificial layers in the first fin structure and the second sacrificial layers in the third fin structure. The method includes forming a first metal gate stack and a second metal gate stack to wrap around each of the first semiconductor layers in the first fin structure and each of the second semiconductor layers in the third fin structure, respectively.

公开(公告)号：US20220028999A1

公开(公告)日：2022-01-27

申请号：US16935061

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Sheng-Tsung Wang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

公开(公告)号：US20220028743A1

公开(公告)日：2022-01-27

申请号：US16935830

申请日：2020-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Li-Zhen Yu ,  Yi-Hsun Chiu ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.

公开(公告)号：US20210408247A1

公开(公告)日：2021-12-30

申请号：US17091159

申请日：2020-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

公开(公告)号：US20210391477A1

公开(公告)日：2021-12-16

申请号：US16898717

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lo-Heng Chang ,  Jung-Hung Chang ,  Zhi-Chang Lin ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.

公开(公告)号：US11195936B2

公开(公告)日：2021-12-07

申请号：US16881685

申请日：2020-05-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L29/51

Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.

公开(公告)号：US20210375858A1

公开(公告)日：2021-12-02

申请号：US17199777

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Kuan-Ting Pan ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L21/762

Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.

公开(公告)号：US11164961B2

公开(公告)日：2021-11-02

申请号：US16686475

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/82 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238

Abstract: A method includes receiving a substrate; forming on the substrate a semiconductor fin; an isolation structure surrounding the semiconductor fin; and first and second dielectric fins above the isolation structure and sandwiching the semiconductor fin; depositing a spacer feature filling spaces between the semiconductor fin and the first and second dielectric fins; performing an etching process to recess the semiconductor fin, resulting in a trench between portions of the spacer feature; and epitaxially growing a semiconductor material in the trench.