公开(公告)号：US20210082740A1

公开(公告)日：2021-03-18

申请号：US17106859

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chang Sun ,  Akira Mineji ,  Ziwei Fang

IPC: H01L21/764 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/266

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.

公开(公告)号：US10861751B2

公开(公告)日：2020-12-08

申请号：US16687152

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Chia Ping Lo ,  Liang-Gi Yao ,  Weng Chang ,  Yee-Chia Yeo ,  Ziwei Fang

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/268 ,  H01L21/324 ,  H01L29/66

Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate, and forming a first layer including a first material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer, wherein performing the anneal process includes adjusting an energy applied to the first layer during the anneal process. The gap is filled by a portion of the first material around the gap reaching a sub-melt temperature that is different from a melting point of the first material.

公开(公告)号：US20200335599A1

公开(公告)日：2020-10-22

申请号：US16946736

申请日：2020-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Kai Tak Lam ,  Sai-Hooi Yeong ,  Chi On Chui ,  Ziwei Fang

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/768

Abstract: A semiconductor structure that includes a semiconductor fin disposed over a substrate, S/D features disposed over the semiconductor fin, and a metal gate stack interposed between the S/D features. The metal gate stack includes a gate dielectric layer disposed over the semiconductor fin, a capping layer disposed over the gate dielectric layer, and a gate electrode disposed over the capping layer, where the gate dielectric layer includes hafnium oxide with hafnium atoms and oxygen atoms arranged in a Pca21 space group.

公开(公告)号：US10811253B2

公开(公告)日：2020-10-20

申请号：US16281723

申请日：2019-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/51 ,  H01L29/40 ,  H01L27/088

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming an interfacial layer on a substrate, and depositing a gate dielectric layer on the interfacial layer. The method also includes treating the gate dielectric layer with a first post deposition annealing (PDA) process. The method further includes depositing a first capping layer on the gate dielectric layer, and treating the gate dielectric layer by performing a post metal annealing (PMA) process on the first capping layer. In addition, the method includes removing the first capping layer, and treating the gate dielectric layer with a second PDA process. The method also includes forming a gate electrode layer on the gate dielectric layer.

公开(公告)号：US10720431B1

公开(公告)日：2020-07-21

申请号：US16258004

申请日：2019-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/308 ,  H01L21/02

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure including a stack of alternating first and second semiconductor layers on a substrate, removing the first semiconductor layers to form spaces between the second semiconductor layers, and depositing a gate dielectric layer to surround the second semiconductor layers. The method also includes depositing a first oxygen blocking layer and removing the native oxide thereof, depositing an n-type work function layer, and forming a second oxygen blocking layer in sequence on the gate dielectric layer to surround the second semiconductor layers in the same process chamber. The second oxygen blocking layer includes a capping layer and a capping film. The method further includes forming a metal gate fill material over the capping film to form a gate-all-around structure.

公开(公告)号：US10686074B2

公开(公告)日：2020-06-16

申请号：US15893081

申请日：2018-02-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung Tsai ,  Shahaji B. More ,  Cheng-Yi Peng ,  Yu-Ming Lin ,  Kuo-Feng Yu ,  Ziwei Fang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/165 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/027 ,  H01L21/3105 ,  H01L29/36 ,  H01L29/161

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure extended above a substrate and a gate structure formed over a middle portion of the fin structure. The middle portion of the fin structure is wrapped by the gate structure. The FinFET device structure includes a source/drain (S/D) structure adjacent to the gate structure, and the S/D structure includes a doped region at an outer portion of the S/D structure, and the doped region includes gallium (Ga). The FinFET device structure includes a metal silicide layer formed over the doped region of the S/D structure, and the metal silicide layer is in direct contact with the doped region of the S/D structure.

公开(公告)号：US10685867B2

公开(公告)日：2020-06-16

申请号：US16173492

申请日：2018-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Tsu-Hsiu Perng ,  Ziwei Fang

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/285

Abstract: A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.

公开(公告)号：US20200135879A1

公开(公告)日：2020-04-30

申请号：US16363109

申请日：2019-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L29/49 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.

公开(公告)号：US20200098623A1

公开(公告)日：2020-03-26

申请号：US16297117

申请日：2019-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/522 ,  H01L23/532

Abstract: A first conductive feature has a dielectric layer formed thereover. An opening is formed in the dielectric layer to expose a portion of the first conductive feature. A first barrier layer is formed over the first conductive feature and over a top surface of the dielectric layer. A second barrier layer is formed over the first barrier layer and on sidewalls of the opening. The second barrier layer is removed, resulting in at least a portion of the first barrier layer disposed over the first conductive feature. A second conductive feature is formed over the portion of the first barrier layer. Sidewalls of the second conductive feature directly contact the dielectric layer.

公开(公告)号：US20200020784A1

公开(公告)日：2020-01-16

申请号：US16578360

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/265

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.