公开(公告)号：US07596173B2

公开(公告)日：2009-09-29

申请号：US11260665

申请日：2005-10-28

申请人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： H04B3/46

CPC分类号： H03K5/13 ,  G01R31/31709 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/16

摘要： There is provided a clock generator for generating a single-phase clock into which jitter has been injected, having a multi-phase clock generating section for generating a plurality of clock signals having an almost equal phase difference from each other and a jitter injecting section for injecting jitter into the respective clock signals.

摘要翻译： 提供了一种时钟发生器，用于产生已经注入了抖动的单相时钟，具有用于产生彼此具有几乎相等的相位差的多个时钟信号的多相时钟产生部分，以及用于 将抖动注入相应的时钟信号。

公开(公告)号：US07541815B2

公开(公告)日：2009-06-02

申请号：US11371939

申请日：2006-03-10

申请人： Kiyotaka Ichiyama ,  Masahiro Ishida ,  Takahiro Yamaguchi

发明人： Kiyotaka Ichiyama ,  Masahiro Ishida ,  Takahiro Yamaguchi

IPC分类号： G01R31/02

CPC分类号： G01R31/3191 ,  G01R31/31926 ,  G01R31/31928

摘要： A testing apparatus tests the performance of an electronic device having an operation circuit for providing a useful output signal. A demodulator configured to provide a phase or frequency demodulated signal related to the output of the operation circuit is packaged with the operation circuit. The gain of the demodulator is controllable from outside the package. The testing apparatus analyses the demodulated signal and controls the gain of the demodulator.

摘要翻译： 测试装置测试具有用于提供有用输出信号的操作电路的电子设备的性能。 配置成提供与操作电路的输出相关的相位或频率解调信号的解调器与操作电路封装。 解调器的增益可从封装外部控制。 测试装置分析解调信号并控制解调器的增益。

公开(公告)号：US07399171B2

公开(公告)日：2008-07-15

申请号：US11259059

申请日：2005-10-27

申请人： Takahiro Yamaguchi ,  Takashi Satou ,  Shigeki Torii ,  Toshiya Hayashi ,  Akihiro Yada ,  Hitoshi Mizutani ,  Takuya Fukitsuke ,  Kazunori Uchiyama ,  Naoki Hakamada

发明人： Takahiro Yamaguchi ,  Takashi Satou ,  Shigeki Torii ,  Toshiya Hayashi ,  Akihiro Yada ,  Hitoshi Mizutani ,  Takuya Fukitsuke ,  Kazunori Uchiyama ,  Naoki Hakamada

IPC分类号： F04C18/00

CPC分类号： B60T8/4031 ,  F04C2/086 ,  F04C2/102 ,  F04C15/06

摘要： The curvature of a circular arc constituted by a side of a suction groove is made larger than that of a circular arc constituted by a side of a discharge groove. Thus, when the suction groove and the discharge groove are viewed in the axial direction of a drive shaft, the distance between the suction groove and the discharge groove in the radial direction of a rotary portion is short in a region intersecting with a line W perpendicular to a centerline, and increases in accordance with a decrease in distance from containment portions. It is therefore possible to ensure a sufficient distance between the discharge and suction grooves and enhance a total fluid pressure generated therebetween, and the contact surface pressure that is necessitated by a second side plate to obtain a press-back force when being in contact with an outer rotor and an inner rotor is reduced.

摘要翻译： 由吸引槽的一侧构成的圆弧的曲率比由排出槽的一侧构成的圆弧的曲率大。 因此，当在驱动轴的轴向上观察吸入槽和排出槽时，旋转部的径向方向上的吸入槽和排出槽之间的距离在垂直于线W的区域中短 到中心线，并且随着距离容纳部分的距离的减小而增加。 因此，可以确保排出和吸入槽之间的足够的距离，并增强其间产生的总的流体压力，以及当与第二侧板接触时获得压靠力所需的接触表面压力 外转子和内转子减少。

公开(公告)号：US07398169B2

公开(公告)日：2008-07-08

申请号：US11362536

申请日：2006-02-27

申请人： Takahiro Yamaguchi ,  Satoshi Iwamoto ,  Masakatsu Suda ,  Masahiro Ishida

发明人： Takahiro Yamaguchi ,  Satoshi Iwamoto ,  Masakatsu Suda ,  Masahiro Ishida

IPC分类号： G06F19/00

CPC分类号： G01R31/31709

摘要： There is provided a measuring apparatus for measuring a signal-under-test, having a comparator for sequentially comparing voltage values of the signal-under-test with a reference voltage value fed thereto at timing of strobe signals sequentially fed thereto, a strobe timing generator for sequentially generating the strobe signals placed almost at equal time intervals, a capture memory for storing the comparison result of the comparator and a digital signal processing section for calculating jitter of the signal-under-test based on the comparison result stored in the capture memory.

摘要翻译： 提供了一种用于测量被测信号的测量装置，具有一个比较器，用于在顺序地馈送到其中的选通信号的定时顺序地比较被测信号的电压值与馈送给它的基准电压值，选通定时发生器 用于顺序地产生几乎以相等的时间间隔放置的选通信号，用于存储比较器的比较结果的捕获存储器和用于基于存储在捕获存储器中的比较结果来计算待测信号的抖动的数字信号处理部分 。

公开(公告)号：USD564994S1

公开(公告)日：2008-03-25

申请号：US29287287

申请日：2007-07-19

申请人： Takahiro Yamaguchi

设计人： Takahiro Yamaguchi

公开(公告)号：US20080040060A1

公开(公告)日：2008-02-14

申请号：US11623101

申请日：2007-01-15

申请人： Harry Hou ,  Takahiro Yamaguchi

发明人： Harry Hou ,  Takahiro Yamaguchi

IPC分类号： G06F19/00 ,  G06F15/00

CPC分类号： G01R31/31725 ,  G01R31/31937

摘要： A measuring apparatus that measures signal-under-test of which signal level is changed at a predetermined bit time interval is provided. The measuring apparatus includes: a strobe timing generator that sequentially generates strobes arranged at substantially even time intervals; a level comparison section that detects the level of the signal-under-test at a timing at which each strobe is sequentially provided; a capture memory that stores therein the signal level outputted by the level comparison section; and a digital signal processing section that calculates a measurement result of the signal-under-test based on data series including data which have substantially even time intervals and each of which interval is larger than a bit time interval of the signal-under-test. The measuring apparatus may include a logical comparison section that outputs a comparison result indicating whether the logical value detected by the level comparison section is corresponding to an expected value and a memory that stores therein the comparison result outputted by the logical comparison section instead of the capture memory. In this case, the digital signal processing section derives the measurement result of the signal-under-test from the comparison result stored in the memory.

摘要翻译： 提供测量信号电平以预定位时间间隔改变的测试信号的测量装置。 测量装置包括：选通定时发生器，其顺序地产生以基本均匀的时间间隔布置的选通; 电平比较部，其在顺序提供每个频闪的定时检测被测信号的电平; 捕获存储器，其中存储由所述电平比较部分输出的信号电平; 以及数字信号处理部，其基于包括具有基本上均匀的时间间隔并且每个间隔大于被测信号的位时间间隔的数据的数据序列来计算待测信号的测量结果。 测量装置可以包括逻辑比较部分，其输出指示由电平比较部分检测到的逻辑值是否对应于预期值的比较结果，以及存储器，其中存储由逻辑比较部分输出的比较结果，而不是捕获 记忆。 在这种情况下，数字信号处理部根据存储在存储器中的比较结果导出测试信号的测量结果。

公开(公告)号：US07317309B2

公开(公告)日：2008-01-08

申请号：US10862904

申请日：2004-06-07

申请人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

发明人： Takahiro Yamaguchi ,  Masahiro Ishida ,  Mani Soma

IPC分类号： G01R23/00 ,  G01R13/00 ,  G10L21/00

CPC分类号： G01R23/16 ,  G01R29/26 ,  G01R31/31709

摘要： A wideband signal analyzing apparatus for analyzing an input signal includes frequency-shifting means for generating a plurality of intermediate frequency signals by shifting a frequency of the input signal as much as respectively different frequency-shifting amounts, so that if a frequency band of the input signal is divided into a plurality of frequency bands, each of the frequency bands can be shifted to a predetermined intermediate band, spectrum measuring means for outputting a complex spectrum of each of the intermediate frequency signals, and spectrum reconstructing means for merging the complex spectra.

摘要翻译： 用于分析输入信号的宽带信号分析装置包括频移装置，用于通过将输入信号的频率分别移动到分别不同的频移量来产生多个中频信号，使得如果输入的频带 信号被分成多个频带，每个频带可以移动到预定的中间频带，用于输出每个中频信号的复谱的频谱测量装置和用于合并复谱的频谱重建装置。

公开(公告)号：US07313496B2

公开(公告)日：2007-12-25

申请号：US11056330

申请日：2005-02-11

申请人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

发明人： Masahiro Ishida ,  Takahiro Yamaguchi ,  Mani Soma

IPC分类号： G01D3/00 ,  G01R27/28

CPC分类号： G01R31/31709 ,  G01R31/2882 ,  G01R31/31716

摘要： A testing apparatus for testing a device under test (DUT) includes a performance board; a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT based on an output signal output by the DUT; a pin electronics between the main frame and the performance board and performs sending and receiving signals between the main frame and the DUT; a deterministic jitter injecting unit for receiving the output signal without passing through the pin electronics and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through the pin electronics; and a switching unit for determining whether the input pin of the DUT is provided with the test signal output by the pin electronics or the loop signal output by the deterministic jitter injecting unit.

摘要翻译： 用于测试被测设备（DUT）的测试设备包括一个性能板; 用于产生用于测试DUT的测试信号和根据DUT输出的输出信号确定DUT的通过/失败的主框架; 在主框架和执行板之间的引脚电子设备，并在主框架和DUT之间执行发送和接收信号; 确定性抖动注入单元，用于在不通过引脚电子装置的情况下接收输出信号，并将作为所注入的确定性抖动的接收输出信号的环路信号输入到DUT的输入引脚，而不通过引脚电子器件; 以及用于确定DUT的输入引脚是否具有由引脚电子器件输出的测试信号或由确定性抖动注入单元输出的环路信号的开关单元。

公开(公告)号：US07225378B2

公开(公告)日：2007-05-29

申请号：US11238822

申请日：2005-09-28

申请人： Masahiro Ishida ,  Takahiro Yamaguchi

发明人： Masahiro Ishida ,  Takahiro Yamaguchi

IPC分类号： G06F11/00 ,  G06F17/50

CPC分类号： G01R31/2882 ,  G01R31/31813 ,  G01R31/3183 ,  G01R31/318328 ,  G01R31/31917 ,  G06F11/263

摘要： A test pattern sequence to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared. One of the faults is selected and an initialization test pattern v1 which establishes an initial value for activating the fault at the location of a fault is determined by an implication operation. A propagation test pattern v2 which causes a stuck-at fault to be propagated to a following gate is determined by another implication operation. A sequence formed by v1 and v2 is registered with a test pattern list and the described operations are repeated until there remains no unprocessed fault in the fault list.

摘要翻译： 用于测试伴随IC发生延迟的延迟故障或开路故障的测试模式序列容易且快速地产生。 准备了可能发生故障的电路内诸如逻辑门和信号线之类的位置列表。 选择其中一个故障，并通过暗示操作确定在故障位置确定激活故障的初始值的初始化测试模式v 1。 通过另一个含义操作来确定导致卡住故障传播到跟随门的传播测试图案v 2。 由v 1和v 2形成的序列用测试图案列表注册，并且重复所描述的操作，直到故障列表中没有未处理的故障。

公开(公告)号：US07225377B2

公开(公告)日：2007-05-29

申请号：US11239414

申请日：2005-09-28

申请人： Masahiro Ishida ,  Takahiro Yamaguchi

发明人： Masahiro Ishida ,  Takahiro Yamaguchi

IPC分类号： G06F11/00 ,  G06F17/50

CPC分类号： G01R31/2882 ,  G01R31/31813 ,  G01R31/3183 ,  G01R31/318328 ,  G01R31/31917 ,  G06F11/263

摘要： Selected test pattern sequences to be used in transient power supply current testing to detect path delay faults in an IC are easily and rapidly generated. A stored fault list of path delay faults is prepared. A train of transition signal values is calculated by simulation of transitions occurring in the IC when a test pattern sequence is applied to the IC, and respective path delay fault in the stored fault list is determined whether it is a detectable fault that is capable of being detected by the transient power supply current testing by using the transition signal values. Those detectable faults that exist in the stored fault list are deleted from the stored fault list and those test pattern sequences that are used to detect the detectable faults existing in the stored fault list are registered in a test pattern sequence list as the selected test pattern sequence.