公开(公告)号：US07398169B2

公开(公告)日：2008-07-08

申请号：US11362536

申请日：2006-02-27

申请人： Takahiro Yamaguchi ,  Satoshi Iwamoto ,  Masakatsu Suda ,  Masahiro Ishida

发明人： Takahiro Yamaguchi ,  Satoshi Iwamoto ,  Masakatsu Suda ,  Masahiro Ishida

IPC分类号： G06F19/00

CPC分类号： G01R31/31709

摘要： There is provided a measuring apparatus for measuring a signal-under-test, having a comparator for sequentially comparing voltage values of the signal-under-test with a reference voltage value fed thereto at timing of strobe signals sequentially fed thereto, a strobe timing generator for sequentially generating the strobe signals placed almost at equal time intervals, a capture memory for storing the comparison result of the comparator and a digital signal processing section for calculating jitter of the signal-under-test based on the comparison result stored in the capture memory.

摘要翻译： 提供了一种用于测量被测信号的测量装置，具有一个比较器，用于在顺序地馈送到其中的选通信号的定时顺序地比较被测信号的电压值与馈送给它的基准电压值，选通定时发生器 用于顺序地产生几乎以相等的时间间隔放置的选通信号，用于存储比较器的比较结果的捕获存储器和用于基于存储在捕获存储器中的比较结果来计算待测信号的抖动的数字信号处理部分 。

公开(公告)号：US20070203659A1

公开(公告)日：2007-08-30

申请号：US11362536

申请日：2006-02-27

申请人： Takahiro Yamaguchi ,  Satoshi Iwamoto ,  Masakatsu Suda ,  Masahiro Ishida

发明人： Takahiro Yamaguchi ,  Satoshi Iwamoto ,  Masakatsu Suda ,  Masahiro Ishida

IPC分类号： G06F19/00

CPC分类号： G01R31/31709

摘要： There is provided a measuring apparatus for measuring a signal-under-test, having a comparator for sequentially comparing voltage values of the signal-under-test with a reference voltage value fed thereto at timing of strobe signals sequentially fed thereto, a strobe timing generator for sequentially generating the strobe signals placed almost at equal time intervals, a capture memory for storing the comparison result of the comparator and a digital signal processing section for calculating jitter of the signal-under-test based on the comparison result stored in the capture memory.

摘要翻译： 提供了一种用于测量被测信号的测量装置，具有一个比较器，用于在顺序地馈送到其中的选通信号的定时顺序地比较被测信号的电压值与馈送给它的基准电压值，选通定时发生器 用于顺序地产生几乎以相等的时间间隔放置的选通信号，用于存储比较器的比较结果的捕获存储器和用于基于存储在捕获存储器中的比较结果来计算待测信号的抖动的数字信号处理部分 。

公开(公告)号：US08427188B2

公开(公告)日：2013-04-23

申请号：US12838428

申请日：2010-07-16

申请人： Satoshi Iwamoto

发明人： Satoshi Iwamoto

IPC分类号： G01R31/26

CPC分类号： G01R31/31932

摘要： There is provided a test apparatus for testing a device under test, including a signal supply section that supplies a test signal to the device under test via a transmission line, and a comparing and judging section that receives a response signal from the device under test via the transmission line shared with the signal supply section, and judges whether the device under test is acceptable by referring to a comparison result obtained by comparing a signal level of the response signal with a reference level corresponding to a logic pattern of the test signal.

摘要翻译： 提供了一种用于测试被测设备的测试装置，包括：通过传输线向被测设备提供测试信号的信号提供部分;以及比较判断部分，其从被测设备接收响应信号， 传输线路与信号提供部分共用，并且通过参考通过将响应信号的信号电平与对应于测试信号的逻辑模式的参考电平进行比较而获得的比较结果来判断被测设备是否可接受。

公开(公告)号：US20090317955A1

公开(公告)日：2009-12-24

申请号：US12551848

申请日：2009-09-01

申请人： Nobuyoshi TAKAHASHI ,  Satoshi Iwamoto ,  Fumihiko Noro ,  Masatoshi Arai

发明人： Nobuyoshi TAKAHASHI ,  Satoshi Iwamoto ,  Fumihiko Noro ,  Masatoshi Arai

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/823878 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573 ,  H01L29/792 ,  Y10S438/954

摘要： A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.

摘要翻译： 一种半导体器件包括形成在半导体衬底上的存储器部分，并且包括具有可存储半导体衬底和存储电极之间的电荷的ONO膜的第一晶体管和用于隔离第一晶体管的第一STI区域和形成在 半导体衬底并且包括具有CMOS电极和栅极电介质的第二晶体管和用于隔离第二晶体管的第二STI区域。 第一STI区域的顶表面的高度被设定为等于或小于第二STI区域的顶表面的高度。

公开(公告)号：US07598589B2

公开(公告)日：2009-10-06

申请号：US11152114

申请日：2005-06-15

申请人： Nobuyoshi Takahashi ,  Satoshi Iwamoto ,  Fumihiko Noro ,  Masatoshi Arai

发明人： Nobuyoshi Takahashi ,  Satoshi Iwamoto ,  Fumihiko Noro ,  Masatoshi Arai

IPC分类号： H01L27/105

CPC分类号： H01L27/11568 ,  H01L21/823878 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573 ,  H01L29/792 ,  Y10S438/954

摘要： A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.

摘要翻译： 一种半导体器件包括形成在半导体衬底上的存储器部分，并且包括具有可存储半导体衬底和存储电极之间的电荷的ONO膜的第一晶体管和用于隔离第一晶体管的第一STI区域和形成在 半导体衬底并且包括具有CMOS电极和栅极电介质的第二晶体管和用于隔离第二晶体管的第二STI区域。 第一STI区域的顶表面的高度被设定为等于或小于第二STI区域的顶表面的高度。

公开(公告)号：US6094085A

公开(公告)日：2000-07-25

申请号：US121953

申请日：1998-07-24

申请人： Toshiyuki Okayasu ,  Satoshi Iwamoto

发明人： Toshiyuki Okayasu ,  Satoshi Iwamoto

IPC分类号： H03K17/14

CPC分类号： H03K17/14

摘要： A driver circuit having a temperature correction circuit for producing an output signal with high precision amplitude and timing by correcting the temperature changes in the amplitude and timing. The temperature correction circuit includes a temperature detector for detecting the temperature change in output elements, a timing adjustment circuit for correcting the timing of an output signal relative to an input signal upon receiving the temperature detection signal from the temperature detector, and a bias circuit for correcting the output amplitude and impedance of the output signal.

摘要翻译： 一种具有温度校正电路的驱动器电路，用于通过校正幅度和定时的温度变化来产生具有高精度振幅和定时的输出信号。 温度校正电路包括用于检测输出元件温度变化的温度检测器，用于在接收到来自温度检测器的温度检测信号时相对于输入信号校正输出信号的定时的定时调整电路，以及用于 校正输出信号的输出振幅和阻抗。

公开(公告)号：US5973542A

公开(公告)日：1999-10-26

申请号：US913350

申请日：1998-02-09

申请人： Toshiyuki Okayasu ,  Satoshi Iwamoto

发明人： Toshiyuki Okayasu ,  Satoshi Iwamoto

IPC分类号： G01R31/319 ,  H03K5/00 ,  H03K5/003 ,  H03K17/14 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

CPC分类号： G01R31/31924 ,  H03K19/00384

摘要： A driver circuit having a temperature correction circuit for providing a relatively stable output amplitude and timing by detecting electric consumption of an output stage of the driver circuit and correcting the changes in the amplitude and timing of an output signal therefrom. The temperature correction circuit includes a temperature detection part for detecting temperature change in a pair of output elements, an output timing temperature correction part for correcting the output timing of the output signal relative to an input signal upon receiving the temperature detection signal from the temperature detection part, and an output amplitude and impedance temperature correction part for correcting output amplitudes and output impedance of the output signal.

摘要翻译： PCT No.PCT / JP97 / 00103 Sec。 371日期：1998年2月9日 102（e）1998年2月9日PCT 1997年1月20日PCT PCT。 出版物WO97 / 33370 日期1997年9月12日具有温度校正电路的驱动器电路，用于通过检测驱动电路的输出级的电耗来校正输出信号的幅度和定时的变化来提供相对稳定的输出幅度和定时。 温度校正电路包括用于检测一对输出元件中的温度变化的温度检测部分，输出定时温度校正部分，用于在从温度检测器接收到温度检测信号时相对于输入信号校正输出信号的输出定时 输出幅度和阻抗温度校正部分，用于校正输出信号的输出幅度和输出阻抗。

公开(公告)号：US08405415B2

公开(公告)日：2013-03-26

申请号：US12557478

申请日：2009-09-10

申请人： Satoshi Iwamoto ,  Koichi Yatsuka

发明人： Satoshi Iwamoto ,  Koichi Yatsuka

IPC分类号： G01R31/26

CPC分类号： G01R31/31907

摘要： Provided is a test apparatus that tests a device under test, comprising a plurality of test modules that test the device under test; a synchronization module that is connected to each of the plurality of test modules, and that synchronizes the plurality of test modules; and a test control section that is connected to the plurality of test modules and the synchronization module, and that controls the test modules and the synchronization module. The synchronization module includes a receiving section that receives, from each of the plurality of test modules, a state signal indicating a state of the test module; an aggregating section that generates an aggregate state signal by calculating an aggregate of the state signals received by the receiving section; and a transmitting section that transmits, to the plurality of test modules, a control signal ordering an operation corresponding to the aggregate state signal.

摘要翻译： 提供了一种测试被测设备的测试设备，包括测试被测设备的多个测试模块; 同步模块，其连接到所述多个测试模块中的每一个，并且使所述多个测试模块同步; 以及连接到所述多个测试模块和所述同步模块并且控制所述测试模块和所述同步模块的测试控制部分。 所述同步模块包括从所述多个测试模块中的每一个接收指示所述测试模块的状态的状态信号的接收部分; 聚合部分，其通过计算由所述接收部分接收的所述状态信号的聚合来生成聚合状态信号; 以及发送部，其向所述多个测试模块发送排序对应于所述聚合状态信号的操作的控制信号。

公开(公告)号：US08362791B2

公开(公告)日：2013-01-29

申请号：US12557468

申请日：2009-09-10

申请人： Motoo Ueda ,  Satoshi Iwamoto ,  Masaru Goishi ,  Hiroyasu Nakayama ,  Masaru Tsuto

发明人： Motoo Ueda ,  Satoshi Iwamoto ,  Masaru Goishi ,  Hiroyasu Nakayama ,  Masaru Tsuto

IPC分类号： G01R31/28 ,  G01R31/00

CPC分类号： G01R31/31907 ,  G01R31/31905

摘要： A test apparatus includes: test modules that communicate with the device under test to test the device under test; additional modules connected between the device under test and the test modules, each additional module performing a communication with the device under test, the communication being at least one of a communication performed at a higher speed and a communication performed with a lower latency, in comparison with a communication performed by the test modules; a test head having a plurality of connectors that connect the test modules and the additional modules, respectively, the test modules and the additional modules are mounted on the test head; a performance board placed on the test head that connects between at least a part of terminals of the plurality of connectors and the device under test. The test modules are connected to the additional modules without through the performance board.

摘要翻译： 测试装置包括：与被测设备通信的测试模块，以测试被测设备; 连接在被测设备和测试模块之间的附加模块，每个附加模块与被测设备进行通信，所述通信是以较高速度执行的通信和以较低延迟执行的通信中的至少一个，相比之下 与测试模块进行通信; 测试头具有分别连接测试模块和附加模块的多个连接器，测试模块和附加模块安装在测试头上; 放置在测试头上的性能板，其连接在多个连接器的至少一部分端子和被测设备之间。 测试模块通过性能板连接到附加模块。

公开(公告)号：US20100102840A1

公开(公告)日：2010-04-29

申请号：US12557468

申请日：2009-09-10

申请人： Motoo UEDA ,  Satoshi Iwamoto ,  Masaru Goishi ,  Hiryoyasu Nakayama ,  Masaru Tsuto

发明人： Motoo UEDA ,  Satoshi Iwamoto ,  Masaru Goishi ,  Hiryoyasu Nakayama ,  Masaru Tsuto

IPC分类号： G01R31/02

CPC分类号： G01R31/31907 ,  G01R31/31905

摘要： A test apparatus includes: test modules that communicate with the device under test to test the device under test; additional modules connected between the device under test and the test modules, each additional module performing a communication with the device under test; the communication being at least one of a communication performed at a higher speed and a communication performed with a lower latency, in comparison with a communication performed by the test modules; a test head having a plurality of connectors that connect the test modules and the additional modules, respectively, the test modules and the additional modules are mounted on the test head; a performance board placed on the test head that connects between at least a part of terminals of the plurality of connectors and the device under test. The test modules are connected to the additional modules without through the performance board.

摘要翻译： 测试装置包括：与被测设备通信的测试模块，以测试被测设备; 连接在被测设备和测试模块之间的附加模块，每个附加模块与被测设备进行通信; 所述通信是与由所述测试模块执行的通信相比较，以较高速度执行的通信和以较低延迟执行的通信中的至少一个通信; 测试头具有分别连接测试模块和附加模块的多个连接器，测试模块和附加模块安装在测试头上; 放置在测试头上的性能板，其连接在多个连接器的至少一部分端子和被测设备之间。 测试模块通过性能板连接到附加模块。