公开(公告)号：US20140028367A1

公开(公告)日：2014-01-30

申请号：US13556579

申请日：2012-07-24

申请人： YU-MENG CHAUNG ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

发明人： YU-MENG CHAUNG ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

IPC分类号： H03K5/06

CPC分类号： H03K17/145 ,  H03K19/00384 ,  H03K2005/00026

摘要： An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.

摘要翻译： 集成电路包括输出缓冲器和控制电路。 输出缓冲器具有信号输入，信号输出和一组控制输入。 输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。 控制电路连接到输出缓冲器的一组控制输入。 控制电路使用第一和第二定时信号来产生控制信号，并且包括产生具有参考延迟的第一定时信号的参考延迟电路，以及延迟仿真电路，其产生与第二定时信号相关的仿真延迟 输出缓冲区延迟。

公开(公告)号：US08638636B2

公开(公告)日：2014-01-28

申请号：US12816960

申请日：2010-06-16

申请人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C8/00

CPC分类号： G11C16/16

摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.

摘要翻译： 该技术的一个实施例是一种装置，存储器集成电路。 存储器集成电路具有字线地址解码电路。 该电路允许选择单个字线以具有擦除电压。 解码器电路包括反相器和逻辑。 逆变器具有输入和控制字线的输出以执行擦除操作。 输入的电压范围在第一参考电压和第二电压基准之间延伸。 电压基准的示例是电压源和地。 在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。 解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。

公开(公告)号：US08630128B2

公开(公告)日：2014-01-14

申请号：US13523060

申请日：2012-06-14

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C7/22

摘要： An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

摘要翻译： 集成电路包括串行外设接口存储器件。 在一个实施例中，存储器件包括时钟信号，多个引脚和配置寄存器。 在一个实施例中，配置寄存器包括等待周期计数。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时向存储器件发送读取地址。 在一个实施例中，读地址至少包括第一地址位和第二地址位，第一地址位使用第一输入/输出引脚发送，第二地址位使用第二输入/输出引脚发送。 该方法包括访问与该地址相关联的数据的存储设备，并等待与等待周期计数相关联的预定数量的时钟周期。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时从存储器件传送数据。

公开(公告)号：US20130214820A1

公开(公告)日：2013-08-22

申请号：US13845576

申请日：2013-03-18

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Nai-Ping Kuo ,  Ming-Chih Hsieh

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Nai-Ping Kuo ,  Ming-Chih Hsieh

IPC分类号： H03K3/00

CPC分类号： H03K3/00 ,  H03K19/0002 ,  H03K19/09425

摘要： An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.

摘要翻译： 集成电路装置包括适于从内部或外部驱动器接收信号的焊盘以及包括耦合到焊盘的输入端的输入缓冲电路。 输入缓冲器电路包括具有控制端子的传输晶体管，连接到焊盘的第一导电端子和连接到第一电压的第二导电端子。 输入缓冲电路还包括具有电耦合到传输晶体管的控制端的端子的锁存器。 所述输入缓冲器电路还包括耦合到所述锁存器的电路，所述电路包括反馈晶体管，所述反馈晶体管具有电耦合到所述焊盘的控制端子，电耦合到第二电压的第一导电端子以及耦合到所述锁存器的第二导电端子。

公开(公告)号：US08374007B2

公开(公告)日：2013-02-12

申请号：US12820422

申请日：2010-06-22

申请人： Chih-Ting Hu ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Wu-Chin Peng ,  Kuen-Long Chang ,  Ken-Hui Chen

发明人： Chih-Ting Hu ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Wu-Chin Peng ,  Kuen-Long Chang ,  Ken-Hui Chen

IPC分类号： H02M7/25 ,  H02M7/00

CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M2001/0032 ,  Y02B70/16

摘要： A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing.

摘要翻译： 提供电源装置和供电方法。 用于具有第一功率信号的系统中的装置包括辅助单元和电源装置。 辅助单元选择性地输出根据第一功率信号的至少一个维持信号。 电源装置输出第二电力信号，其中电源装置根据至少一个维持信号维持第二电力信号，例如处于非空闲状态，例如空闲或待机状态或其他合适的定时。

公开(公告)号：US20120092937A1

公开(公告)日：2012-04-19

申请号：US13282116

申请日：2011-10-26

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C7/22

摘要： A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

摘要翻译： 一种用于在包括串行外设接口存储器件的集成电路中读取的双I / O数据的方法。 在一个实施例中，存储器件包括时钟信号，多个引脚和配置寄存器。 在一个实施例中，配置寄存器包括等待周期计数。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时向存储器件发送读取地址。 在一个实施例中，读地址至少包括第一地址位和第二地址位，第一地址位使用第一输入/输出引脚发送，第二地址位使用第二输入/输出引脚发送。 该方法包括访问与该地址相关联的数据的存储设备，并等待与等待周期计数相关联的预定数量的时钟周期。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时从存储器件传送数据。

公开(公告)号：US20110317493A1

公开(公告)日：2011-12-29

申请号：US12826280

申请日：2010-06-29

申请人： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/04

CPC分类号： G11C11/5635 ,  G11C16/0483 ,  G11C16/3418

摘要： Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

摘要翻译： 各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线 第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

公开(公告)号：US08085611B2

公开(公告)日：2011-12-27

申请号：US12545793

申请日：2009-08-21

申请人： Yung Feng Lin ,  Kuen-Long Chang ,  Chun Hsiung Hung

发明人： Yung Feng Lin ,  Kuen-Long Chang ,  Chun Hsiung Hung

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G11C16/28

摘要： Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.

摘要翻译： 通过使用扭曲的数据线和差分感测放大器来减轻耦合到相邻数据线的非易失性存储器中的数据线上的过度擦除感应噪声。 耦合到数据线中的噪声由耦合到参考数据线中的相似噪声补偿并在差分感测放大器中被消除。

公开(公告)号：US20110227552A1

公开(公告)日：2011-09-22

申请号：US12820422

申请日：2010-06-22

申请人： Chih-Ting Hu ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Wu-Chin Peng ,  Kuen-Long Chang ,  Ken-Hui Chen

发明人： Chih-Ting Hu ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Wu-Chin Peng ,  Kuen-Long Chang ,  Ken-Hui Chen

IPC分类号： G05F3/02

CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M2001/0032 ,  Y02B70/16

摘要： A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing.

摘要翻译： 提供电源装置和供电方法。 用于具有第一功率信号的系统中的装置包括辅助单元和电源装置。 辅助单元选择性地输出根据第一功率信号的至少一个维持信号。 电源装置输出第二电力信号，其中电源装置根据至少一个维持信号维持第二电力信号，例如处于非空闲状态，例如空闲或待机状态或其他合适的定时。

公开(公告)号：US20110038218A1

公开(公告)日：2011-02-17

申请号：US12911173

申请日：2010-10-25

申请人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

发明人： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

IPC分类号： G11C29/08

CPC分类号： G11C29/022 ,  G11C29/02

摘要： A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

摘要翻译： 提供了一种存储芯片及其操作方法。 存储器芯片包括多个焊盘。 该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。