公开(公告)号：US20050141058A1

公开(公告)日：2005-06-30

申请号：US11015242

申请日：2004-12-17

Applicant: Jeffrey Raynor

Inventor： Jeffrey Raynor

IPC: G01N21/25 ,  G01N21/27 ,  G01N21/64 ,  G01N21/75 ,  H04N1/04

CPC classification number: G01N21/6454 ,  G01N21/253 ,  G01N21/274 ,  G01N21/6428 ,  G01N21/75

Abstract: A bio-optical sensor has a surface provided with an array of sensing pixels and calibration pixels. The sensing and calibration pixels are arranged in an interleaved fashion. The sensing and calibration pixels may be interleaved 1:1, or they may be arranged in interleaved blocks. The image plane receives an analyte and a reagent that reacts with the analyte to produce light. The sensing pixels generate signals as a function of the light produced.

Abstract translation: 生物光学传感器具有设置有感测像素和校准像素阵列的表面。 感测和校准像素以交错方式排列。 感测和校准像素可以交织1：1，或者它们可以被布置在交错块中。 图像平面接收分析物和与分析物反应产生光的试剂。 感测像素产生作为产生的光的函数的信号。

公开(公告)号：US20040188728A1

公开(公告)日：2004-09-30

申请号：US10781977

申请日：2004-02-19

Applicant: STMicroelectronics Ltd.

Inventor： Lindsay Grant

IPC: H01L031/062 ,  H01L031/113 ,  C30B001/00 ,  H01L021/20 ,  H01L021/36

CPC classification number: H01L27/14609 ,  H01L27/1462

Abstract: A CMOS image sensor and method for making such a sensor includes a coating over the photosensing parts, wherein the coating performs a dual function. In fabrication, the coating prevents the formation of silicide, which is not optically opaque, on the photosensing parts. When the CMOS sensor is in use, the coating helps to couple light onto the photosensing parts, and therefore acts as an anti-reflective layer. The method of fabrication uses a self-aligning technique, which ensures pixel-to-pixel uniformity.

Abstract translation: 用于制造这种传感器的CMOS图像传感器和方法包括在光敏部件上的涂层，其中涂层执行双重功能。 在制造中，涂层防止在光敏部件上形成不是光学不透明的硅化物。 当使用CMOS传感器时，涂层有助于将光耦合到光敏部件上，因此用作抗反射层。 制造方法使用自对准技术，其确保像素到像素的均匀性。

公开(公告)号：US20040027470A1

公开(公告)日：2004-02-12

申请号：US10407871

申请日：2003-04-04

Applicant: STMicroelectronics Ltd

Inventor： Robert Henderson ,  Jonathan Ephriam David Hurwitz

IPC: H04N005/335

CPC classification number: H04N5/3653 ,  H04N5/3575

Abstract: An image sensor has an array of pixels read by column circuits to provide reset and read samples on a pair of sample capacitors. To alleviate the effects of parasitic capacitance in the region of the sample capacitors, a modified timing arrangement is used. Both sample switches are operated simultaneously to pre-charge both sample capacitors with a pixel signal value. One sample switch is operated after reset to apply a reset value to one of the pre-charged sample capacitors.

Abstract translation: 图像传感器具有由列电路读取的像素阵列，以在一对采样电容器上提供复位和读取样本。 为了减轻样品电容器区域中的寄生电容的影响，使用修正的定时装置。 两个采样开关同时工作，以预先给像素信号值的两个采样电容器预充电。 一个采样开关在复位后运行，将一个复位值应用于一个预充电采样电容。

公开(公告)号：US20030227040A1

公开(公告)日：2003-12-11

申请号：US10405101

申请日：2003-04-01

Applicant: STMicroelectronics Ltd

Inventor： Robert Henderson

IPC: H01L031/062

CPC classification number: H04N5/3575 ,  H04N5/363 ,  H04N5/374

Abstract: A solid state image sensor has an array of pixels in which each column has a reset voltage line and a read line. The sensor is reset and read a row at a time, with reset-related values held in a frame buffer for subsequent subtraction from read values. Reset-related values are derived in each column by sampling the voltage during reset on one capacitor and the voltage on release of reset on a second capacitor, and differencing these values to provide an output for the frame buffer. This provides a reduction in the size of frame buffer which would otherwise be required.

Abstract translation: 固态图像传感器具有其中每列具有复位电压线和读取线的像素阵列。 传感器一次复位并读取一行，复位相关值保持在帧缓冲器中，以便随后从读取值中减去。 通过在一个电容器的复位期间对电压进行采样，在第二个电容器上进行复位时的电压，并对这些值进行差分以提供帧缓冲器的输出，从而在每列中得到复位相关值。 这样可以减少否则将需要的帧缓冲区的大小。

公开(公告)号：US20030020531A1

公开(公告)日：2003-01-30

申请号：US10206135

申请日：2002-07-26

Applicant: STMicroelectronics Ltd.

Inventor： Rajesh Kaushik

IPC: H03K017/16

CPC classification number: H03K17/166

Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.

Abstract translation: CMOS输出缓冲器使用来自接地节点的反馈，通过利用可容忍的接地反弹限制来减少接地反弹，使其对工作条件和处理参数的敏感性降低。 输出缓冲器的NMOS器件的输入由从接地节点接收来自预驱动器的第一输入和第二输入（即，反馈）的控制元件的输出提供。

公开(公告)号：US20030020522A1

公开(公告)日：2003-01-30

申请号：US10099588

申请日：2002-03-13

Applicant: STMicroelectronics, Ltd.

Inventor： Andrew Dellow

IPC: H04L027/06 ,  H04L007/00

CPC classification number: H03K23/68 ,  H03K21/10 ,  H03K23/66

Abstract: A digital frequency divider has a single circulating shifter register loaded with a bit sequence of variable length and having two outputs adjacent such that are output is equal to the other delayed by one clock period. The outputs are passed to a multiplexer via further logic, the multiplexer selecting one of two inputs depending on whether a clock is high or low. Program logic is provided so that the circuit is configurable for odd, even or half integer division by detecting changes in the bit sequence between 0 and 1 and selectively nulldeletingnull the first half clock cycle when a change is detected. This allows even, odd or half integer clock division with an nullevennull mark space ratio.

Abstract translation: 数字分频器具有单个循环移位寄存器，其加载可变长度的位序列，并且具有相邻的两个输出，使得输出等于另一个延迟一个时钟周期。 输出通过另外的逻辑被传送到多路复用器，多路复用器根据时钟是高还是低选择两个输入之一。 提供程序逻辑，使得通过检测0和1之间的位序列的变化，并且当检测到改变时选择性地“删除”前半个时钟周期，电路可配置为奇，偶或半整数除法。 这允许偶数，奇数或半整数时钟分频与“偶数”标记空间比。

公开(公告)号：US20020194449A1

公开(公告)日：2002-12-19

申请号：US10172355

申请日：2002-06-14

Applicant: STMicroelectronics Ltd.

Inventor： Ankur Bal

IPC: G06F009/34

CPC classification number: H03K19/17728

Abstract: A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.

Abstract translation: 提供了一种用于减少实现布尔函数所需的查找表中可编程体系结构元素数量或相同或逻辑等价的操作的系统。 该系统可以包括连接到多个解码器的输入的单组存储元件，并且存储元件可以由解码器同时访问以向其提供同时多个输出。

公开(公告)号：US20020079491A1

公开(公告)日：2002-06-27

申请号：US10008606

申请日：2001-12-06

Applicant: STMicroelectronics Ltd

Inventor： Jeff Raynor

IPC: H01L031/20 ,  H01L031/0376 ,  H01L031/036 ,  H01L029/04

CPC classification number: H01L27/14627

Abstract: A solid state image sensor includes an array of pixels and a corresponding array of microlenses. The positions of the microlenses relative to their corresponding pixels may vary according to the distances of the pixels from a central optical axis of the image sensor to substantially eliminate vignetting of light collected by the microlenses.

Abstract translation: 固态图像传感器包括像素阵列和相应的微透镜阵列。 微透镜相对于其对应像素的位置可以根据像素与图像传感器的中心光轴的距离而变化，以基本上消除由微透镜收集的光的渐晕。

公开(公告)号：US20020010841A1

公开(公告)日：2002-01-24

申请号：US09972548

申请日：2001-10-05

Applicant: STMicroelectronics, Ltd.

Inventor： Fabrizio Rovati

IPC: G06F013/00

CPC classification number: G06F13/1678

Abstract: There is disclosed a method and circuit for allowing access to a shared memory by at least two controllers having different bus widths. Such method and circuit provides particular advantages in its application to controlling access to a shared memory in a digital set-top-box of a digital television receiver. An arbiter is provided to access between memory accesses by first and second memory access circuitry. The first memory access circuitry accesses a block of data in the shared memory, and the second memory access circuitry accesses two blocks of data in each memory access. Each second memory write access comprises reading blocks of data from first and second memory locations and then writing blocks of data to first and second memory locations.

Abstract translation: 公开了一种用于允许具有不同总线宽度的至少两个控制器访问共享存储器的方法和电路。 这种方法和电路在其用于控制​​对数字电视接收机的数字机顶盒中的共享存储器的访问方面提供了特别的优点。 提供仲裁器以访问由第一和第二存储器访问电路进行的存储器访问。 第一存储器访问电路访问共享存储器中的数据块，并且第二存储器访问电路在每个存储器访问中访问两个数据块。 每个第二存储器写访问包括从第一和第二存储器位置读取数据块，然后将数据块写入第一和第二存储器位置。

公开(公告)号：US5959465A

公开(公告)日：1999-09-28

申请号：US581737

申请日：1995-12-29

Applicant: Robert Beat

Inventor： Robert Beat

IPC: H03K19/177

CPC classification number: H03K19/1772

Abstract: A method is provided for operating a programmable logic array in an integrated circuit. Each stage of the circuit is enabled only during the time necessary for that stage to propagate an incoming signal. Enable signals are generated for the stages of the circuit, using a dummy circuit which replicates elements of the circuit in dimension, orientation and connectivity. These elements provide a delay path, such that an input signal applied coincidentally to the programmable logic array circuit and the dummy circuit produces outputs of the dummy circuit which define times for applying and removing the enable signals from stages of the programmable logic array circuit.

Abstract translation: 提供了一种用于在集成电路中操作可编程逻辑阵列的方法。 电路的每一级仅在该级传播输入信号所需的时间内被使能。 使用在电路的尺寸，方向和连接性上复制电路元件的虚拟电路产生电路级的使能信号。 这些元件提供延迟路径，使得与可编程逻辑阵列电路同时施加的输入信号和虚拟电路产生虚拟电路的输出，该输出定义用于从可编程逻辑阵列电路的级施加和去除使能信号的时间。