公开(公告)号：US3293607A

公开(公告)日：1966-12-20

申请号：US14742261

申请日：1961-10-20

申请人： KALBFELL DAVID C

发明人： KALBFELL DAVID C

IPC分类号： H04L27/152

CPC分类号： H04L27/152

公开(公告)号：US11817891B2

公开(公告)日：2023-11-14

申请号：US17460710

申请日：2021-08-30

申请人： Samsung Electronics Co., Ltd.

发明人： Youngbaek Choi

IPC分类号： H04B1/00 ,  H04L27/152 ,  H04L5/00 ,  H04L27/00

CPC分类号： H04B1/0064 ,  H04B1/0067 ,  H04L5/001 ,  H04L27/0014 ,  H04L27/152 ,  H04L2027/0016

摘要： An electronic device and a method performed by an electronic device are provided. A number of frequency bands of a plurality of carriers to be used in a plurality of communication circuits for communication is determined. The plurality of communication circuits process carrier signals in different frequency bands. A switching operation, performed by at least one switch, is controlled based on the number of frequency bands and a specified condition that is based on frequency bands able to be processed by an LNA included in each of the plurality of communication circuits. The carrier signals of the plurality of carriers is processed using at least one communication circuit. The at least one switch is alternately connected to two communication circuits and is configured to provide a reception carrier signal from at least one antenna to one of the two communication circuits based on a switching operation.

公开(公告)号：US20220200782A1

公开(公告)日：2022-06-23

申请号：US17481357

申请日：2021-09-22

申请人： Intel Corporation

发明人： Elan BANIN ,  Evgeny SHUMAKER ,  Ofir DEGANI ,  Rotem BANIN ,  Shahar GROSS

IPC分类号： H04L7/033 ,  H04L27/22 ,  H04L27/152

摘要： A wireless communication device for asymmetrical frequency spreading including a processor configured to receive a frequency band message comprising a maximum difference and a minimum difference, wherein the maximum difference is between a maximum frequency of a sub-band and a signal frequency, and wherein the minimum difference is between the minimum frequency of the sub-band and the signal frequency compare the maximum difference and the minimum difference with each other; and generate a frequency shift based on the comparison.

公开(公告)号：US20220006676A1

公开(公告)日：2022-01-06

申请号：US17115805

申请日：2020-12-09

申请人： RichWave Technology Corp.

发明人： Ching Shou Huang

IPC分类号： H04L27/152 ,  H04L7/033 ,  H03L7/099

摘要： A frequency modulation demodulation device and a control method thereof are provided. The frequency modulation demodulation device includes an input terminal, a phase converter, a phase-locked loop circuit, and a frequency offset/shift detector. The input terminal receives an input signal. The phase converter is coupled to the input terminal and receives the input signal to obtain a phase signal. The phase-locked loop circuit is coupled to the phase converter to generate a phase adjustment signal according to the phase signal, and the phase-locked loop circuit adjusts the phase signal according to the phase adjustment signal to perform demodulation of the input signal. The frequency offset/shift detector is coupled to the phase-locked loop circuit and generates a frequency offset/shift determining signal according to the phase adjustment signal obtained from the phase-locked loop circuit. The frequency offset/shift determining signal is related to a phase frequency offset/shift of the input signal.

公开(公告)号：US10790911B2

公开(公告)日：2020-09-29

申请号：US16380452

申请日：2019-04-10

申请人： The University of Massachusetts

发明人： Yifei Li

IPC分类号： H04B10/61 ,  G02F1/035 ,  H04L27/152 ,  H04B10/25 ,  G02F1/025

摘要： A Sagnac loop coherent phase modulated RF photonic link employing an ACP-OPLL linear phase demodulator was presented. This structure demonstrated stable signal transmission over a 1-km long coherent RF photonic link.

公开(公告)号：US10749593B2

公开(公告)日：2020-08-18

申请号：US15233830

申请日：2016-08-10

申请人： California Institute of Technology

发明人： Seyed Ali Hajimiri ,  Florian Bohn ,  Behrooz Abiri

IPC分类号： H03F3/04 ,  H04B7/185 ,  H03F3/19 ,  H02S40/30 ,  H03F3/68 ,  H03F1/02 ,  H03F3/45 ,  H03F3/24 ,  B64G1/42 ,  H04B7/06 ,  H04L25/08 ,  H04L27/152 ,  H04L27/26

摘要： Many embodiments of the invention include stacked power amplifier configurations that include control circuitry for sensing the operational characteristics of the power amplifiers and adjusting the current drawn by one or more of the power amplifiers to prevent any of the power amplifiers from experiencing over voltage stresses and/or to increase the operational efficiency of the power amplifiers.

公开(公告)号：US10608853B1

公开(公告)日：2020-03-31

申请号：US16130087

申请日：2018-09-13

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Yogesh Darwhekar ,  Pranav Kumar ,  Arpan Thakkar ,  Naveen Mahadev ,  Srikanth Manian

IPC分类号： H04L27/00 ,  H04L27/38 ,  H04L27/152 ,  H04L27/148

摘要： A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.

公开(公告)号：US10541737B2

公开(公告)日：2020-01-21

申请号：US16061467

申请日：2015-12-22

申请人： Telefonaktiebolaget LM Ericsson (publ)

发明人： Henrik Sjöland ,  Tony Påhlsson

IPC分类号： H04B7/06 ,  H03L7/099 ,  H03L7/097 ,  H04L27/152 ,  H03L7/087 ,  H04B1/04 ,  H04B1/16 ,  H03L7/089

摘要： A phase locked loop, particularly for or in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and a second feedback signal (FBD) in response to an oscillator signal (FO), the second feedback signal (FBD) delayed with respect to the first feedback signal (FB); a first comparator path (4) configured to receive the first feedback signal (FB) and a second comparator path (5) configured to receive the second feedback signal (FBD), each of the first and second comparator path (4, 5) configured to provide a respective current signal (CS1, CS2) to the loop filter (1) in response to a respective adjustment signal (FA1, FA2) and a phase deviation between a common reference signal (FR) and the respective feedback signal (FB, FBD).

公开(公告)号：US10447282B2

公开(公告)日：2019-10-15

申请号：US15863672

申请日：2018-01-05

申请人： QUALCOMM Incorporated

发明人： John Abcarius

IPC分类号： H03L7/089 ,  H03L7/093 ,  H04L27/152 ,  H04L27/148

摘要： A phase locked loop (PLL) includes a first charge pump coupled to a filter. The first charge pump may feed the filter a first current. A second charge pump is coupled to the filter. The second charge pump may feed the filter a second current. A first gate is coupled to an input of the second charge pump. The first gate selectively gates the second current.

公开(公告)号：US20190157015A1

公开(公告)日：2019-05-23

申请号：US16167799

申请日：2018-10-23

申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

发明人： Clark T.-C. Nguyen ,  Ruonan Liu ,  Jalal Naghsh Nilchi

IPC分类号： H01H1/00 ,  H04L27/152 ,  H03K5/135

摘要： A microelectromechanical resonant switch (“resoswitch”) converts received radio frequency (RF) energy into a clock output. The resoswitch first accepts incoming amplitude- or frequency-shift keyed clock-modulated RF energy at a carrier frequency, filters it, provides power gain via resonant impact switching, and finally envelop detects impact impulses to demodulate and recover the carrier clock waveform. The resulting output derives from the clock signal that originally modulated the RF carrier, resulting in a local clock that shares its originator's accuracy. A bare push-pull 1-kHz RF-powered mechanical clock generator driving an on-chip inverter gate capacitance of 5 fF can potentially operate with only 5 pW of battery power, 200,000 times lower than a typical real-time clock. Using an off-chip inverter with 17.5 pF of effective capacitance, a 1-kHz push-pull resonator would consume 17.5 nW.