公开(公告)号：US07391087B2

公开(公告)日：2008-06-24

申请号：US09475452

申请日：1999-12-30

Applicant: Anand Murthy ,  Robert S. Chau ,  Patrick Morrow

Inventor： Anand Murthy ,  Robert S. Chau ,  Patrick Morrow

IPC: H01L27/148

CPC classification number: H01L29/66628 ,  H01L21/28052 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636

Abstract: An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and to define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.

Abstract translation: 一种MOS器件，包括在第一导电类型区域上形成的栅极电介质。 形成在栅极电介质上的栅电极。 沿着栅电极的横向相对的侧壁形成一对侧壁间隔物。 一对沉积的硅或硅合金源极/漏极区域形成在栅电极的第一导电区域和相对侧上，其中硅或硅合金源极/漏极区域在栅极电极下方延伸并且限定在栅电极下方的沟道区域 第一导电类型区域中的栅极电极，其中栅电极正下方的沟道区域大于深入所述第一导电类型区域的沟道区域。

公开(公告)号：US20070105331A1

公开(公告)日：2007-05-10

申请号：US11643523

申请日：2006-12-21

Applicant: Anand Murthy ,  Glenn Glass ,  Andrew Westmeyer ,  Michael Hattendorf ,  Jeffrey Wank

Inventor： Anand Murthy ,  Glenn Glass ,  Andrew Westmeyer ,  Michael Hattendorf ,  Jeffrey Wank

IPC: H01L21/331

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7834

Abstract: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.

Abstract translation: 本发明增加了替代源极 - 漏极cMOS晶体管的技术。 方法可以包括使用一个设备组来蚀刻衬底材料中的凹部，然后在另一个设备组中进行沉积。 公开了一种在没有大气暴露的情况下在相同的反应器中进行蚀刻和随后的沉积的方法。 用于替代源极 - 漏极应用的源极 - 漏极凹槽的原位蚀刻提供了与现有技术的非原位蚀刻相比的几个优点。 晶体管驱动电流通过以下因素得到改善：（1）当蚀刻后的表面暴露于大气中时，消除硅 - 外延层界面的污染，（2）精确控制蚀刻凹槽的形状。 沉积可以通过各种技术进行，包括选择性和非选择性方法。 在覆盖层沉积的情况下，还提出了避免在性能关键区域中无定形沉积的措施。

公开(公告)号：US06885084B2

公开(公告)日：2005-04-26

申请号：US10626257

申请日：2003-07-23

Applicant: Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

Inventor： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

公开(公告)号：US06861318B2

公开(公告)日：2005-03-01

申请号：US10626365

申请日：2003-07-23

Applicant: Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

Inventor： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract translation: 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IDSAT和IDLIN。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

公开(公告)号：US06797556B2

公开(公告)日：2004-09-28

申请号：US10338371

申请日：2003-01-07

Applicant: Anand Murthy ,  Robert S. Chau ,  Patrick Morrow

Inventor： Anand Murthy ,  Robert S. Chau ,  Patrick Morrow

IPC: H01L2972

CPC classification number: H01L29/66628 ,  H01L21/28052 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636

Abstract: An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and to define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.

Abstract translation: 一种MOS器件，包括形成在第一导电类型区域上的栅极电介质。 形成在栅极电介质上的栅电极。 沿着栅电极的横向相对的侧壁形成一对侧壁间隔物。 一对沉积的硅或硅合金源极/漏极区域形成在栅电极的第一导电区域和相对侧上，其中硅或硅合金源极/漏极区域在栅极电极下方延伸并且限定在栅电极下方的沟道区域 第一导电类型区域中的栅极电极，其中栅电极正下方的沟道区域大于深入所述第一导电类型区域的沟道区域。

公开(公告)号：US06579771B1

公开(公告)日：2003-06-17

申请号：US10013225

申请日：2001-12-10

Applicant: Shahriar Ahmed ,  Mark Bohr ,  Stephen Chambers ,  Richard Green ,  Anand Murthy

Inventor： Shahriar Ahmed ,  Mark Bohr ,  Stephen Chambers ,  Richard Green ,  Anand Murthy

IPC: H01L218228

CPC classification number: H01L29/66287

Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

Abstract translation: 本发明涉及一种形成双极结型晶体管（BJT）的方法，其包括在衬底上形成拓扑结构。 此后，在拓扑形成间隔物。 基底层由间隔物上方的外延硅和拓扑形成。 通过从间隔物的扩散形成在衬底中的泄漏块结构。 此后，BJT完成了基层和隔离层。