公开(公告)号：US08098227B2

公开(公告)日：2012-01-17

申请号：US12338182

申请日：2008-12-18

Applicant: Hong-Woo Lee ,  Jong-Hwan Lee ,  Beom-Jun Kim ,  Sung-Man Kim ,  Gyu-Tae Kim ,  Kyoung-Jun Jang

Inventor： Hong-Woo Lee ,  Jong-Hwan Lee ,  Beom-Jun Kim ,  Sung-Man Kim ,  Gyu-Tae Kim ,  Kyoung-Jun Jang

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G11C19/184 ,  H03K17/165

Abstract: A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval.

Abstract translation: 栅极驱动电路包括级联级，每级包括上拉部分，进位部分，上拉驱动部分，保持部分和逆变器。 上拉部分将输入时钟的栅极电压上拉。 进位部分将输入电压提升到输入时钟。 上拉驱动部分连接到与进位部分和上拉部分相同的控制端子（Q-节点），并且从前一级接收先前的进位电压以打开上拉部分和进位 部分。 保持部将栅极电压保持在截止电压，逆变器基于逆变器时钟来控制保持部的开启和关闭保持部中的至少一个。 给定水平周期（1H）中的高电平的反相器时钟在时间上在预定时间间隔的输入时钟的高电平之前。

公开(公告)号：US20100158188A1

公开(公告)日：2010-06-24

申请号：US12575895

申请日：2009-10-08

Applicant: Hong-Woo LEE ,  Sung-Man KIM ,  Jong-Hyuk LEE ,  Jong-Hwan LEE ,  Hyeon-Hwan KIM ,  Sang-Moon MOH ,  Jeong-Il KIM ,  Yeon-Kyu MOON

Inventor： Hong-Woo LEE ,  Sung-Man KIM ,  Jong-Hyuk LEE ,  Jong-Hwan LEE ,  Hyeon-Hwan KIM ,  Sang-Moon MOH ,  Jeong-Il KIM ,  Yeon-Kyu MOON

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2300/0408

Abstract: A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.

Abstract translation: 上拉驱动部分通过响应于前一级或垂直启动信号之一接收导通电压而将第一节点的信号保持在高电平。 上拉部分响应于第一节点的信号通过输出端子输出时钟信号。 当第一节点的信号分别为低或高时，第一保持部件将第二节点的信号保持在高电平或低电平。 第二保持部分响应于第二节点的信号或延迟和反相的时钟信号，将第一节点的信号和输出端的信号保持在接地电压。

公开(公告)号：US07719008B2

公开(公告)日：2010-05-18

申请号：US11496320

申请日：2006-07-31

Applicant: Do Gi Lim ,  Jong Hwan Lee ,  Hong Woo Lee ,  Yong Jo Kim ,  Yong Woo Lee

Inventor： Do Gi Lim ,  Jong Hwan Lee ,  Hong Woo Lee ,  Yong Jo Kim ,  Yong Woo Lee

IPC: H01L31/20

CPC classification number: H01L27/1222 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1288

Abstract: A thin film transistor substrate, wherein the moving area of electrons between source and drain electrodes of a thin film transistor (TFT) is minimized, the moving distance of electrons is increased, and the sizes of capacitors defined by a gate electrode together with the respective source and drain electrodes are identical to each other so that an off current generated when the TFT is off can be minimized; a method of manufacturing the thin film transistor substrate; and a mask for manufacturing the thin film transistor substrate. Accordingly, it is possible to minimize an off current induced due to a phenomenon of electron trapping by light.

Abstract translation: 一种薄膜晶体管基板，其中薄膜晶体管（TFT）的源极和漏极之间的电子的移动面积最小化，电子的移动距离增加，并且由栅电极限定的电容器的尺寸与相应的 源极和漏极彼此相同，使得当TFT截止时产生的截止电流可以最小化; 制造薄膜晶体管基板的方法; 以及用于制造薄膜晶体管基板的掩模。 因此，可以将由于光的电子俘获现象引起的截止电流最小化。

公开(公告)号：US20100056623A1

公开(公告)日：2010-03-04

申请号：US11814809

申请日：2005-01-26

Applicant: Sang Joon Lee ,  Soon Kil Ahn ,  Hong Woo Lee ,  Joong Bok Ahn ,  Jae Soo Shin ,  Young Min Kwon

Inventor： Sang Joon Lee ,  Soon Kil Ahn ,  Hong Woo Lee ,  Joong Bok Ahn ,  Jae Soo Shin ,  Young Min Kwon

IPC: A61K31/336 ,  C07D305/14 ,  A61P35/00

CPC classification number: C07D303/28

Abstract: The present invention relates to a fumagillol derivative, pharmaceutically acceptable salts thereof and a method for preparing the same. The compounds of the present invention can be prepared through acylation, hydrolysis and alkylation. The compound of the present invention can be prepared in the form of a pharmaceutically acceptable salt or inclusion compound. The present invention provides fumagillol derivatives having the following characteristics: increased inhibiting effect on angiogenesis, low toxicity, excellent solubility and chemical stability as compared to conventional angiogenesis inhibitors. The compounds of the present invention can be used as an anti-cancer medicine, inhibitor of cancer metastasis, or the therapeutic agent for treating rheumatic arthritis, psoriasis, diabetic retinitis or obesity.

Abstract translation: 本发明涉及烟曲霉醇衍生物，其药学上可接受的盐及其制备方法。 本发明的化合物可以通过酰化，水解和烷基化制备。 本发明的化合物可以以药学上可接受的盐或包合物的形式制备。 本发明提供具有以下特征的烟曲霉醇衍生物：与常规血管生成抑制剂相比，增加对血管发生的抑制作用，低毒性，优异的溶解性和化学稳定性。 本发明的化合物可以用作抗癌药物，癌症转移抑制剂，或用于治疗风湿性关节炎，牛皮癣，糖尿病性视网膜炎或肥胖症的治疗剂。

公开(公告)号：US20090040203A1

公开(公告)日：2009-02-12

申请号：US12218814

申请日：2008-07-18

Applicant: Sung-Man Kim ,  Hong-Woo Lee ,  Myung-Koo Hur ,  Hee-Joon Kim

Inventor： Sung-Man Kim ,  Hong-Woo Lee ,  Myung-Koo Hur ,  Hee-Joon Kim

IPC: G06F3/038

CPC classification number: G09G3/3677 ,  G09G2310/0286 ,  G11C19/184

Abstract: A gate driving circuit and a display device having the same, a pull-up unit pulls up a current gate signal by using a first clock signal during a first period of one frame. A pull-up driver coupled to the pull-up unit receives a carry signal from one of the previous stages to turn on the pull-up unit. A pull-up unit receives a gate signal from one of the next stages, discharges the current gate signal to an off voltage level, and turns off the pull-up unit. A holder holds the current gate signal at the voltage level. An inverter turns on/off the holder in response to a first clock signal. A ripple preventer has a source and a gate coupled in common to an output terminal of the pull-up unit and a drain coupled to an input terminal of the inverter, and includes a ripple preventing diode for preventing a ripple from being applied to the inverter.

Abstract translation: 一种栅极驱动电路和具有该栅极驱动电路的显示装置，上拉单元在一帧的第一周期期间通过使用第一时钟信号来上拉电流门信号。 耦合到上拉单元的上拉驱动器从前一级之一接收进位信号，以接通上拉单元。 上拉单元接收来自下一级中的一个的门信号，将当前门信号放电至截止电压电平，并关闭上拉单元。 持有者将当前门信号保持在电压电平。 逆变器响应于第一个时钟信号打开/关闭支架。 波纹防止器具有与上拉单元的输出端子共同耦合的源极和栅极，以及耦合到反相器的输入端子的漏极，并且包括用于防止纹波施加到逆变器的纹波防止二极管 。

公开(公告)号：US20080303760A1

公开(公告)日：2008-12-11

申请号：US12043308

申请日：2008-03-06

Applicant: Beom-Jun Kim ,  Hee-Joon Kim ,  Hong-Woo Lee ,  Hye-Rhee Han ,  Hyeong-Jun Park ,  Jin-Suk Seo

Inventor： Beom-Jun Kim ,  Hee-Joon Kim ,  Hong-Woo Lee ,  Hye-Rhee Han ,  Hyeong-Jun Park ,  Jin-Suk Seo

IPC: G09G3/36

CPC classification number: H01L27/124 ,  G02F1/134309 ,  G02F1/136286

Abstract: An array substrate of an LCD having: a gate line formed along a first direction; a data line formed along a second direction crossing the first direction; first and second pixel electrodes spaced apart from each other; a thin-film transistor includes a gate electrode connected to the gate line; a source electrode connected to the data line and partially overlapping the second pixel electrode; and a drain electrode connected to the first pixel electrode spaced apart from the second pixel electrode along the second direction. The source electrode or the gate electrode overlaps the second pixel electrode but the drain electrode does not overlap the second pixel electrode. Electrical coupling between the first and second pixel electrodes are avoided with such configuration.

Abstract translation: 一种LCD的阵列基板，具有沿第一方向形成的栅极线; 沿着与第一方向交叉的第二方向形成的数据线; 第一和第二像素电极彼此间隔开; 薄膜晶体管包括连接到栅极线的栅电极; 源极连接到数据线并部分地与第二像素电极重叠; 以及漏极，其沿着所述第二方向连接到与所述第二像素电极间隔开的所述第一像素电极。 源电极或栅电极与第二像素电极重叠，但漏电极不与第二像素电极重叠。 通过这种配置可以避免第一和第二像素电极之间的电耦合。

公开(公告)号：US20080100760A1

公开(公告)日：2008-05-01

申请号：US11932433

申请日：2007-10-31

Applicant: Hong-Woo LEE ,  Sang-Youn Han ,  Jong-Oh KIM ,  Sang-Yong NO ,  Shin-Tack KANG ,  Hyeong-Jun PARK

Inventor： Hong-Woo LEE ,  Sang-Youn Han ,  Jong-Oh KIM ,  Sang-Yong NO ,  Shin-Tack KANG ,  Hyeong-Jun PARK

IPC: G02F1/1335 ,  G02F1/133 ,  G02F1/1368

CPC classification number: G02F1/133514 ,  G02F1/1362 ,  G02F2201/52

Abstract: In a display device, gate lines, which extend in a first direction, cross and are insulated from data lines, which extend in a second direction, to define pixel areas on a first base substrate. Pixels are arranged in the pixel areas, respectively, and a color filter layer including a plurality of color filter is arranged on a second base substrate that is coupled with the first base substrate. The color filters include a first sub color filter, a second sub color filter, and a third sub color filter, repeatedly arranged in the first direction and the second direction to represent different colors, respectively.

Abstract translation: 在显示装置中，沿着第一方向延伸的栅极线与在第二方向上延伸的数据线交叉并绝缘，以限定第一基板上的像素区域。 像素分别布置在像素区域中，并且包括多个滤色器的滤色器层布置在与第一基底基板耦合的第二基底基板上。 滤色器包括分别沿第一方向和第二方向重复排列以表示不同颜色的第一子滤色器，第二子滤色器和第三子滤色器。

公开(公告)号：US20080048712A1

公开(公告)日：2008-02-28

申请号：US11840471

申请日：2007-08-17

Applicant: Byeong-Jae Ahn ,  Sung-Man Kim ,  Bong-Jun Lee ,  Hong-Woo Lee

Inventor： Byeong-Jae Ahn ,  Sung-Man Kim ,  Bong-Jun Lee ,  Hong-Woo Lee

IPC: H03K17/16

CPC classification number: H03K17/161 ,  G09G3/3677 ,  G11C19/184

Abstract: In a gate driving circuit and a display apparatus having the same, a ripple preventing part is connected to a pull-up part and a control terminal (Q-node) to reset the Q-node. The ripple preventing part includes a first ripple preventing device that resets the Q-node during a high period of the first clock within a (n−1)H period, and a second ripple preventing device that resets the Q-node during a high period of a second clock within the (n−1)H period. A back-flow preventing device is connected between a previous carry node and the second ripple preventing device to prevent an electric charge of the Q-node from flowing back to the previous carry node.

Abstract translation: 在栅极驱动电路和具有该栅极驱动电路的显示装置中，纹波防止部分连接到上拉部分和控制端子（Q-节点）以复位Q-节点。 纹波防止部包括在第（n-1）个H周期内在第一时钟的高周期期间复位Q-节点的第一纹波防止装置和在高周期期间复位Q-节点的第二纹波防止装置 （n-1）个H周期内的第二个时钟。 在前一进位节点和第二纹波防止装置之间连接防回流装置，以防止Q-节点的电荷回流到先前的进位节点。

公开(公告)号：US20080048709A1

公开(公告)日：2008-02-28

申请号：US11881776

申请日：2007-07-26

Applicant: Hong Woo Lee ,  Myung Koo Hur ,  Jong Hwan Lee ,  Sung Man Kim ,  Jong Hyuk Lee

Inventor： Hong Woo Lee ,  Myung Koo Hur ,  Jong Hwan Lee ,  Sung Man Kim ,  Jong Hyuk Lee

IPC: G01R31/00

CPC classification number: G09G3/006 ,  G09G3/3614 ,  G09G3/3648

Abstract: The present invention relates to a module and method for detecting a defect of a thin film transistor (TFT) substrate, which can detect disconnection of a gate line of the TFT substrate having gate drivers provided with a dual structure in which the gate drivers are provided at both sides of the gate lines. There is provided a module and method for detecting a defect of a TFT substrate, wherein gate lines are separated into two portions by cutting a central region of the gate lines, gate power is supplied to the gate lines of which central portions are cut through gate drivers provided at both sides of the gate lines, and a signal of a negative voltage level is supplied to data lines, so that disconnection of the gate lines can be detected.

Abstract translation: 本发明涉及一种用于检测薄膜晶体管（TFT）基板的缺陷的模块和方法，该薄膜晶体管（TFT）基板可以检测具有栅极驱动器的TFT基板的栅极线的断开，该栅极驱动器设置有提供栅极驱动器的双重结构 在门线的两边。 提供了一种用于检测TFT基板的缺陷的模块和方法，其中通过切割栅极线的中心区域将栅极线分成两部分，栅极功率被提供给通过栅极切割中心部分的栅极线 提供在栅极线的两侧的驱动器，并且向数据线提供负电压电平的信号，从而可以检测到栅极线的断开。

公开(公告)号：US20080043191A1

公开(公告)日：2008-02-21

申请号：US11839752

申请日：2007-08-16

Applicant: Sung-Man Kim ,  Myung-Koo Hur ,  Jong-Hwan Lee ,  Yong Woo Lee ,  Hong-Woo Lee ,  Jin-Suk Seo

Inventor： Sung-Man Kim ,  Myung-Koo Hur ,  Jong-Hwan Lee ,  Yong Woo Lee ,  Hong-Woo Lee ,  Jin-Suk Seo

IPC: G02F1/1343

CPC classification number: G02F1/133707

Abstract: Disclosed is a liquid crystal display device including a first substrate, a second substrate, and a liquid crystal layer interposed there between. The first substrate is provided with gate lines and data lines thereon. The gate lines and data lines cross with each other and are insulated from each other. Pixel electrodes are stacked on the gate lines and data lines. Each pixel electrode includes first and second sub-pixel electrodes spaced apart from each other and a connection electrode, which connects the first sub-pixel electrode to the second sub-pixel electrode. The second substrate is provided with a common electrode thereon. The common electrode includes a first domain divider formed on the center of the first sub-pixel electrode and a second domain divider formed on the center of the second sub-pixel electrode.

Abstract translation: 公开了一种液晶显示装置，包括第一基板，第二基板和介于其间的液晶层。 第一基板上设置有栅线和数据线。 栅极线和数据线彼此交叉并且彼此绝缘。 像素电极堆叠在栅极线和数据线上。 每个像素电极包括彼此间隔开的第一和第二子像素电极和将第一子像素电极连接到第二子像素电极的连接电极。 第二基板上设置有公共电极。 公共电极包括形成在第一子像素电极的中心上的第一域分隔器和形成在第二子像素电极的中心的第二域分隔器。