公开(公告)号：US06400542B1

公开(公告)日：2002-06-04

申请号：US09882680

申请日：2001-06-18

Applicant: Jian-Hsing Lee ,  Jian-Ren Shih ,  Yi-Hsun Wu ,  Jing-Meng Liu

Inventor： Jian-Hsing Lee ,  Jian-Ren Shih ,  Yi-Hsun Wu ,  Jing-Meng Liu

IPC: H02H900

CPC classification number: H01L27/0259

Abstract: A voltage clamping circuit that protects integrated circuits having multiple separate power supply voltage terminals from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage terminals. The voltage clamping circuit has two subgroups of Darlington connected clamping transistors. The first subgroup of Darlington connected clamping transistors is connected between the first power supply voltage terminal and the second power supply voltage terminal. If the differential voltage exceeds the first clamping voltage level, the first subgroup of Darlington connected clamping transistors turn on and restore the first differential voltage to a level less than the first clamping voltage level. The second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal. If the differential voltage exceeds the second clamping voltage level, the second subgroup of Darlington connected transistors turn on and restore the differential voltage to a level less than the second clamping voltage level.

Abstract translation: 一种电压钳位电路，当ESD事件在多个分离的电源电压端子之间引起过大的差分电压时，保护具有多个单独的电源电压端子的集成电路免受损坏。 电压钳位电路有两个Darlington连接钳位晶体管的子组。 达林顿连接的钳位晶体管的第一个子组连接在第一电源电压端子和第二电源电压端子之间。 如果差分电压超过第一钳位电压电平，则达林顿连接的钳位晶体管的第一个子组导通，并将第一个差分电压恢复到小于第一钳位电压电平的电平。 连接在第二电源端子和第一电源端子之间的达林顿的第二子组连接钳位晶体管。 如果差分电压超过第二钳位电压电平，则达林顿连接晶体管的第二个子组导通，并将差分电压恢复到小于第二钳位电压电平的电平。

公开(公告)号：US06362035B1

公开(公告)日：2002-03-26

申请号：US09498741

申请日：2000-02-07

Applicant: Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Hsien-Chin Lin

Inventor： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Hsien-Chin Lin

IPC: H01L2144

CPC classification number: H01L21/823878 ,  H01L21/76237 ,  Y10S438/919

Abstract: A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.

Abstract translation: 描述了一种用于在双阱CMOS工艺的场隔离下并入离子注入通道阻挡层的方法，其中该层通过在整个晶片上的覆盖硼离子注入直接放置在完成的场隔离下。 通道停止植入物遵循场氧化物的平坦化，并且因此在场和有源区域中基本上处于相同的深度。 随后，注入的p阱和n阱形成得比沟道阻挡层深，n阱注入量足够高的剂量，以过度补偿沟道阻挡层，从而从n阱中除去它的作用。 在p阱附近的场氧化物下的通道停止注入的一部分提供了有效的抗穿透保护，只有较小的结电容增加。 该方法在利用浅沟槽隔离的工艺中示出并且特别有效。

公开(公告)号：US06358781B1

公开(公告)日：2002-03-19

申请号：US09607043

申请日：2000-06-30

Applicant: Jian-Hsing Lee ,  Kuo-Chio Liu ,  Bing-Lung Liao ,  Jiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Kuo-Chio Liu ,  Bing-Lung Liao ,  Jiaw-Ren Shih

IPC: H01L21332

CPC classification number: H01L27/0266

Abstract: NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.

公开(公告)号：US06190954B1

公开(公告)日：2001-02-20

申请号：US09229381

申请日：1999-01-11

Applicant: Jian-Hsing Lee ,  Shui-Hung Chen ,  Jiaw Ren Shih

Inventor： Jian-Hsing Lee ,  Shui-Hung Chen ,  Jiaw Ren Shih

IPC: H01L218238

CPC classification number: H01L21/823892 ,  H01L27/0921

Abstract: A method is disclosed to provide for more robust latchup-immune CMOS transistors by increasing the breakover voltage VBO, or trigger point, of the parasitic npn and pnp transistors present in CMOS structures. These goals have been achieved by adding a barrier layer to both the n-well and p-well of a twin-well CMOS structure, thus increasing the energy gap for electrons and holes of the parasitic npn and pnp transistor, respectively.

Abstract translation: 公开了一种通过增加存在于CMOS结构中的寄生npn和pnp晶体管的跳转电压VBO或触发点来提供更稳健的闭锁免疫CMOS晶体管的方法。 这些目标已经通过在双井CMOS结构的n阱和p阱两者中添加阻挡层来实现，从而分别增加了寄生npn和pnp晶体管的电子和空穴的能隙。

公开(公告)号：US6055183A

公开(公告)日：2000-04-25

申请号：US957678

申请日：1997-10-24

Applicant: Ming-Chou Ho ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh

Inventor： Ming-Chou Ho ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Juang-Ke Yeh

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16

Abstract: A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles, while preventing damage due to high field stress in the tunneling oxide. The method to erase a flash EEPROM cell begins by applying a relatively high positive voltage pulse to the source of the EEPROM cell. Simultaneously a ground reference voltage is applied to the drain and to the semiconductor substrate. At the same time a relatively large negative voltage pulse is applied to the control gate. This will cause a parasitic bipolar transistor to conduct and go into a snap back condition reducing the voltage field in the tunneling oxide.

Abstract translation: 在快速EEPROM的隧道氧化物中捕获电荷的同时消除闪存EEPROM中的数据的方法，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离，同时防止由于高 隧道氧化物中的场应力。 擦除快闪EEPROM单元的方法是通过向EEPROM单元的源极施加相对高的正电压脉冲开始的。 同时，对漏极和半导体衬底施加接地参考电压。 同时，向控制栅极施加相当大的负电压脉冲。 这将导致寄生双极晶体管导通并进入快速恢复条件，从而减少隧道氧化物中的电压场。

公开(公告)号：US6049486A

公开(公告)日：2000-04-11

申请号：US224982

申请日：1999-01-04

Applicant: Jian-Hsing Lee ,  Kuo-Reay Peng

Inventor： Jian-Hsing Lee ,  Kuo-Reay Peng

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14

Abstract: A multiple phase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate by first applying a first relatively large negative voltage pulse to the control gate. Concurrently a first moderately large positive voltage pulse is applied to the source. Also, concurrently a ground reference potential is applied to the first well and the semiconductor substrate, and the drain and second well are disconnected to allow the drain and second well to float. The flash EEPROM cell is then source erased to further remove charges from the floating gate by floating the drain and the second well and concurrently applying the ground reference potential to the semiconductor substrate, the drain, and the first well. Simultaneously, a relatively large positive voltage pulse is applied to the source. The flash EEPROM is then channel erased to detrap charges from the tunneling oxide by applying a second relatively large negative voltage pulse to the control gate of the EEPROM cell and concurrently applying a second moderately large positive voltage pulse to the first well. At this same time, a ground reference potential is applied to the semiconductor substrate and the drain, the source, and the second well are floated.

Abstract translation: 从闪存EEPROM擦除数据的多相方法可以消除捕获在快速EEPROM的隧道氧化物中的电荷，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除快闪EEPROM单元的方法是通过负栅极擦除开始，以通过首先向控制栅极施加第一相对较大的负电压脉冲来从浮置栅极去除电荷。 同时，第一个适度大的正电压脉冲施加到源。 此外，同时对第一阱和半导体衬底施加接地参考电位，并且漏极和第二阱被断开以允许漏极和第二阱漂浮。 闪速EEPROM单元然后被擦除，以通过浮置漏极和第二阱来进一步从浮置栅极去除电荷，并且同时将接地参考电位施加到半导体衬底，漏极和第一阱。 同时，向源极施加相对较大的正电压脉冲。 然后通过向EEPROM单元的控制栅极施加第二相对较大的负电压脉冲并且同时向第一阱施加第二适度大的正电压脉冲，将闪速EEPROM擦除以从隧道氧化物中去除电荷。 同时，对半导体衬底施加接地参考电位，并且漏极，源极和第二阱浮起。

公开(公告)号：US6025628A

公开(公告)日：2000-02-15

申请号：US253291

申请日：1999-02-19

Applicant: Jian-Hsing Lee ,  Kuo-Reay Peng ,  Jung-Ke Yeh ,  Hsiu-Han Liao

Inventor： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Jung-Ke Yeh ,  Hsiu-Han Liao

IPC: H01L21/336 ,  H01L27/092 ,  H01L29/08 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66575 ,  H01L27/0928 ,  H01L29/0847

Abstract: An FET semiconductor device comprises a doped silicon semiconductor substrate having a surface. The substrate being doped with a first type of dopant. An N-well is formed within the surface of the P-substrate. A P-well is formed within the N-well forming a twin well. Field oxide regions are formed on the surface of the substrate located above borders between the wells and regions of the substrate surrounding the wells. A gate electrode structure is formed over the P-well between the field oxide regions. A source region and a drain region are formed in the surface of the substrate. The source region and the drain region are self-aligned with the gate electrode structure with the source region and the drain region being spaced away from the field oxide regions by a gap of greater than or equal to about 0.7 .mu.m.

Abstract translation: FET半导体器件包括具有表面的掺杂硅半导体衬底。 衬底被掺杂有第一类型的掺杂剂。 在P基板的表面内形成有N阱。 在形成双井的N阱内形成P阱。 位于位于井周围的边界之上的基板的表面上的场氧化物区域和围绕所述孔的基板的区域形成。 在场氧化物区域之间的P阱上形成栅电极结构。 源极区域和漏极区域形成在衬底的表面中。 源极区域和漏极区域与栅极电极结构自对准，源极区域和漏极区域与场氧化物区域间隔开大于或等于约0.7μm的间隙。

公开(公告)号：US5933732A

公开(公告)日：1999-08-03

申请号：US851563

申请日：1997-05-07

Applicant: Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Jian-Hsing Lee

Inventor： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Jian-Hsing Lee

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0441 ,  G11C16/045 ,  H01L27/115 ,  H01L29/7885

Abstract: An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack. A P+ drain region is formed in the surface of the N-region self-aligned with the gate electrode stack.

Abstract translation: FET半导体器件包括形成在衬底中的N区和P区，其中N区与P区并置，具有N区和P区之​​间的界面，并且N区中的第一通道 - 区域和P区域中的第二个通道。 N +漏极区域位于P区域中第一通道一侧的界面附近。 P +漏极区域位于N区域中第二通道一侧的界面附近。 N +源极区域与第一通道的与P区域中的界面相反。 P +源极区域与N区域中的界面在第一通道的相对侧。 宽栅电极EEPROM堆叠桥接N区和P区中的沟道。 堆叠包括隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极。 在与栅电极堆叠自对准的P区的表面中形成N +漏极区。 在与栅极电极堆叠自对准的N区域的表面中形成P +漏极区域。

公开(公告)号：US5891792A

公开(公告)日：1999-04-06

申请号：US133968

申请日：1998-08-14

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee

IPC: H01L21/265 ,  H01L21/336 ,  H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  G03C1/77

CPC classification number: H01L27/027 ,  H01L27/0259 ,  H01L29/1079 ,  H01L29/66477 ,  H01L29/7836 ,  H01L21/26506 ,  H01L21/26586

Abstract: A structure and method for fabricating an ESD device for FET transistors by forming a silicon germanium region 40 under a channel region 44 of a field effect transistor (FET). The silicon germanium region 40 comprises the base of a parasitic bipolar 200 transistor that increases the turn on speed. The method comprises:a) forming a gate dielectric layer 20 over a substrate 10;b) forming a gate 30 over the gate 30; the substrate having a channel region under the gate; the channel region extending from the surface of the substrate to a channel depth below the substrate surface;c) forming a silicon germanium region 40 under the channel region 44 using a tilt angle ion implant of Germanium ions;d) forming source and drain doped regions 50 70 adjacent to the channel region and the silicon germanium region whereby the silicon germanium region comprises a base of a parasitic bipolar transistor 40.

Abstract translation: 一种通过在场效应晶体管（FET）的沟道区44下形成硅锗区40来制造用于FET晶体管的ESD器件的结构和方法。 硅锗区域40包括增加导通速度的寄生双极型200晶体管的基极。 该方法包括：a）在衬底10上形成栅介质层20; b）在门30上形成门30; 所述基板在所述栅极下方具有沟道区域; 所述沟道区域从所述衬底的表面延伸到所述衬底表面下方的沟道深度; c）使用锗离子的倾斜角离子注入在沟道区44下形成硅锗区40; d）形成与沟道区和硅锗区相邻的源极和漏极掺杂区50 70，由此硅锗区包括寄生双极晶体管40的基极。

公开(公告)号：US5862078A

公开(公告)日：1999-01-19

申请号：US907984

申请日：1997-08-11

Applicant: Juang-Ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Ming-Chou Ho

Inventor： Juang-Ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Ming-Chou Ho

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/349

Abstract: A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to detrap the tunneling oxide of the flash EEPROM cell. The channel erasing consists floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a first relatively large negative voltage pulse is applied to the control gate, as a first moderately large positive voltage pulse is applied to said source. The method to erase then proceeds with the source erasing to remove charges from the floating gate of the flash EEPROM cell. The source erasing consists of applying a second relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a second moderately large positive voltage pulse to a first diffusion well. At the same time the ground reference potential continues to be applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float.

Abstract translation: 一种在闪存EEPROM的隧穿氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除快闪EEPROM单元的方法是通过通道擦除来消除快速EEPROM单元的隧道氧化物。 通道擦除包括使漏极和第二扩散阱浮置，同时将接地参考电位施加到半导体衬底和第一扩散阱。 同时，第一相对较大的负电压脉冲施加到控制栅极，因为第一适度大的正电压脉冲被施加到所述源极。 擦除方法随后进行源擦除以从快闪EEPROM单元的浮动栅极去除电荷。 源擦除包括将第二相对较大的负电压脉冲施加到所述EEPROM单元的控制栅并且向第一扩散阱同时施加第二适度大的正电压脉冲。 同时，接地参考电位继续施加到半导体衬底，同时漏极和第二扩散阱被允许浮动。