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    Memory devices and related methods of forming a memory device
    111.
    发明授权
    Memory devices and related methods of forming a memory device 有权

    公开(公告)号：US12261111B2

    公开(公告)日：2025-03-25

    申请号：US18600146

    申请日：2024-03-08

    Applicant: Micron Technology, Inc.

    Inventor： Kunal R. Parekh

    IPC: H01L23/522 ,  G11C7/18 ,  H01L23/00 ,  H01L23/528 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35

    Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.

    Loopback datapath for clock quality detection
    112.
    发明授权
    Loopback datapath for clock quality detection 有权

    公开(公告)号：US12260926B2

    公开(公告)日：2025-03-25

    申请号：US18312280

    申请日：2023-05-04

    Applicant: Micron Technology, Inc.

    Inventor： Matthew Alan Prather ,  Won Ho Choi

    IPC: G11C29/12

    Abstract: Devices and methods include transmitting loopback signals for monitoring operation of a memory device. In some embodiments, a memory device may receive a system clock signal from a host device and may generate an internal clock signal based at least in part on the system clock signal. In some embodiments, the memory device may generate a loopback signal based at least in part on the internal clock signal and may transmit the loopback signal via a loopback datapath associated with the memory device. A host device may compare the internal clock signal and the system clock signal to determine a fidelity of the internal clock signal. Termination values of the memory device may be adjusted based on the determined fidelity of the internal clock signal.

    Artificial neural network bypass
    116.
    发明授权
    Artificial neural network bypass 有权

    公开(公告)号：US12260313B2

    公开(公告)日：2025-03-25

    申请号：US16951768

    申请日：2020-11-18

    Applicant: Micron Technology, Inc.

    Inventor： Saideep Tiku ,  Poorna Kale

    IPC: G06N3/045 ,  G06N3/08

    Abstract: Apparatuses and methods can be related to implementing bypass paths in an ANN. The bypass path can be used to bypass a portion of the ANN such that the ANN generates an output with a particular level of confidence while utilizing less resources than if the portion of the ANN had not been bypassed.

    Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells
    117.
    发明申请
    Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells 有权

    公开(公告)号：US20250096042A1

    公开(公告)日：2025-03-20

    申请号：US18970741

    申请日：2024-12-05

    Applicant: Micron Technology, Inc.

    Inventor： Anilkumar Chandolu ,  Indra V. Chary

    IPC: H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. The memory-block regions comprise part of a memory-plane region. A pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. The pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. Through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines. Other embodiments, including structure independent of method, are disclosed.

    DYNAMIC STEP VOLTAGE LEVEL ADJUSTMENT
    118.
    发明申请
    DYNAMIC STEP VOLTAGE LEVEL ADJUSTMENT 有权

    公开(公告)号：US20250095746A1

    公开(公告)日：2025-03-20

    申请号：US18967011

    申请日：2024-12-03

    Applicant: Micron Technology, Inc.

    Inventor： Carmine Miccoli ,  Andrew Bicksler

    IPC: G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32

    Abstract: Processing logic in a memory device receives a request to execute a programming operation on a set of memory cells of the memory device. A first set of programming pulses corresponding to a first step voltage level are caused to be applied to program the set of memory cells. The processing logic determines that a programming voltage level associated with a programming pulse of the first set of one or more programming pulses satisfies a condition. The first set voltage is adjusted to a second step voltage level in response to the condition being satisfied.

    CAPACITANCE BALANCING IN SEMICONDUCTOR DEVICES
    119.
    发明申请
    CAPACITANCE BALANCING IN SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250095718A1

    公开(公告)日：2025-03-20

    申请号：US18788001

    申请日：2024-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Eric Carman ,  Christopher Morzano

    IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094

    Abstract: Systems, methods, and apparatus are provided for capacitance balancing in semiconductor devices. An apparatus comprising a sense amplifier having first and second nodes and configured to amplify a voltage difference between the first and second nodes. A first global sense line is coupled to the first node and a plurality of first locals sense lines are coupled in parallel to the first global sense line. A second global sense line is coupled to the second node and a plurality of second local sense lines are coupled in parallel to the second global sense line. Control circuitry is configured to electrically connect the selected first local sense line of the plurality of first local sense lines to the first global sense line and electrically connect at least two second local sense lines of the plurality of second local sense lines to the second global sense line.

    APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER CIRCUIT
    120.
    发明申请
    APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER CIRCUIT 有权

    公开(公告)号：US20250095713A1

    公开(公告)日：2025-03-20

    申请号：US18958966

    申请日：2024-11-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

    IPC: G11C11/4076 ,  G11C11/4096

    Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

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