公开(公告)号：US20050207531A1

公开(公告)日：2005-09-22

申请号：US11039331

申请日：2005-01-20

Applicant: James Dempsey ,  Ravindra Ahuja ,  Arvind Kumar ,  Jonathan Li ,  H. Romeijn

Inventor： James Dempsey ,  Ravindra Ahuja ,  Arvind Kumar ,  Jonathan Li ,  H. Romeijn

IPC: A61N5/10

CPC classification number: A61N5/1031 ,  A61N5/1042

Abstract: A method of determining a treatment plan for intensity modulated radiation treatment (IMRT) divides a three-dimensional volume of a patient into a grid of dose voxels. At least a portion of the dose voxels are designated to belong to at least one target or to at least one critical structure. An ionizing radiation dose as delivered by a plurality of beamlets each having a beamlet intensity is modeled. A non-linear convex voxel-based penalty function model is provided for optimizing a fluence map. The fluence map defines the beamlet intensities for each of the plurality of beamlets. The model is then solved based on defined clinical criteria for the target and the critical structure using an interior point algorithm with dense column handling to obtain a globally optimal fluence map.

Abstract translation: 确定强度调制辐射治疗（IMRT）的治疗计划的方法将患者的三维体积分成剂量体素的网格。 剂量体素的至少一部分被指定为属于至少一个靶或至少一个关键结构。 由多个具有子束强度的子束传送的电离辐射剂量被建模。 提供了一种非线性凸基于体素的惩罚函数模型，用于优化注量图。 注量图定义了多个子束中的每一个的子束强度。 然后使用具有密集列处理的内点算法，基于目标和临界结构的定义临床标准来解决该模型，以获得全局最优注量图。

公开(公告)号：US20050091301A1

公开(公告)日：2005-04-28

申请号：US10691922

申请日：2003-10-23

Applicant: Peyman Oreizy ,  Arvind Kumar ,  Mark Schofield ,  Kevin Moore ,  Sean Blagsvedt

Inventor： Peyman Oreizy ,  Arvind Kumar ,  Mark Schofield ,  Kevin Moore ,  Sean Blagsvedt

IPC: G06F15/16 ,  H04L12/58 ,  H04L29/06 ,  H04L29/08

CPC classification number: H04L65/403 ,  H04L29/06027 ,  H04L51/04 ,  H04L65/1043 ,  H04L67/2814 ,  H04L69/329

Abstract: A messaging system is provided whereby a message indicative of an invitation to collaboratively execute an application can be sent from one of the computing object to an intermediary system whereby the message is multicast to the other ones of the plurality of computing objects. The invitation message can be accepted by the other computing objects to cause the first object to launch the corresponding application. The other computing objects also launch versions of the application and exchange addressing information with the first application so that a multiparty application execution can be established.

Abstract translation: 提供消息系统，由此可以将指示协作执行应用的邀请的消息从计算对象之一发送到中间系统，由此将消息多播到多个计算对象中的另一个。 邀请消息可被其他计算对象接受，以使第一个对象启动相应的应用程序。 其他计算对象还启动应用程序的版本并与第一个应用程序交换寻址信息，以便可以建立多方应用程序的执行。

公开(公告)号：US06668335B1

公开(公告)日：2003-12-23

申请号：US09653643

申请日：2000-08-31

Applicant: Scott E. Breach ,  John Eble ,  Arvind Kumar ,  Richard E. Kessler ,  Darrel Donaldson ,  David W. Hartwell

Inventor： Scott E. Breach ,  John Eble ,  Arvind Kumar ,  Richard E. Kessler ,  Darrel Donaldson ,  David W. Hartwell

IPC: G06F104

CPC classification number: H04L45/00 ,  G06F1/10

Abstract: A system comprising a communications link between processors configured to transmit packets between transmitting and receiving processors. The communications link comprises a conduction path for each bit in the packet and the paths are grouped into separate bundles and routed along different paths. A forwarded clock signal is sent with each bundle. The processors operate with a clock frequency that is roughly three times as fast as the clock frequency of the forwarded clock signal. Data is transmitted on both rising and falling edges of the clock. The receiving processor comprises a recovery circuit to which it pulls the asynchronous data into the processor clock domain. The recovery circuit comprises a delay locked loop circuit configured to create a delayed copy of the clock signal with clock edges that are aligned with the center of the data window for the transmitted data.

Abstract translation: 一种系统，包括被配置为在发送和接收处理器之间传送分组的处理器之间的通信链路。 通信链路包括用于分组中的每个比特的传导路径，并且路径被分组成分开的分组并沿着不同的路径路由。 每个包发送转发的时钟信号。 处理器的工作时钟频率大约是转发时钟信号的时钟频率的三倍。 数据在时钟的上升沿和下降沿都传输。 接收处理器包括一个恢复电路，它将异步数据拉入处理器时钟域。 恢复电路包括延迟锁定环路电路，其被配置为创建时钟信号的延迟副本，其中时钟沿与发送数据的数据窗口的中心对准。

公开(公告)号：US06370072B1

公开(公告)日：2002-04-09

申请号：US09726377

申请日：2000-11-30

Applicant: Robert H. Dennard ,  Arvind Kumar

Inventor： Robert H. Dennard ,  Arvind Kumar

IPC: G11C702

CPC classification number: G11C7/067 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/063 ,  G11C2207/2227

Abstract: In a DRAM memory circuit, a current sensing amplifier is provided that exploits the low impedance of a reference transistor biased in the sub-threshold regime to enable transfer of a small voltage swing on the bitline to result in a large voltage signal on a low capacitance sense node. Compared to conventional voltage sensing, reduced bitline-bitline coupling noise results because of the small bitline swing, potentially allowing more cells to be served by a sense amplifier because of weak dependence of sense amplifier on bit-line capacitance. Compared to previous current-sensing schemes, this invention allows no idling current. The current-sensing amplifier additionally may be used in conjunction with a hierarchical bitline scheme to further increase the number of cells served by each sense amplifier.

Abstract translation: 在DRAM存储器电路中，提供电流感测放大器，其利用偏置在子阈值状态中的参考晶体管的低阻抗，以使得能够在位线上传送小的电压摆幅，从而在低电容上产生较大的电压信号 感知节点。 与常规电压感测相比，​​由于位线摆幅小而导致位线位线耦合噪声减小，由于读出放大器对位线电容的弱依赖性，潜在地允许更多的单元由读出放大器提供服务。 与以前的电流检测方案相比，本发明不允许空载电流。 电流检测放大器另外可以与分层位线方案结合使用，以进一步增加由每个读出放大器服务的单元的数量。

公开(公告)号：US5723288A

公开(公告)日：1998-03-03

申请号：US238766

申请日：1994-05-06

Applicant: Christine C. Dykstra ,  Richard R. Tidwell ,  David W. Boykin ,  W. David Wilson ,  Jaroslaw Spychala ,  Bijan P. Das ,  Arvind Kumar

Inventor： Christine C. Dykstra ,  Richard R. Tidwell ,  David W. Boykin ,  W. David Wilson ,  Jaroslaw Spychala ,  Bijan P. Das ,  Arvind Kumar

IPC: G01N33/50 ,  A61K31/505 ,  A61K31/506 ,  C07D307/52 ,  C07D307/54 ,  C07D307/58 ,  C07D403/10 ,  C07D403/14 ,  C07D405/14 ,  C09B23/01 ,  C12Q1/68 ,  G01N21/78 ,  G01N33/52 ,  G01N33/58

CPC classification number: G01N33/52 ,  A61K31/505 ,  A61K31/506 ,  C07D307/54 ,  C07D403/10 ,  C07D403/14 ,  C07D405/14 ,  C09B23/0075 ,  Y10S435/808 ,  Y10S435/81

Abstract: Disclosed is a method of fluorescent detection of a nucleic acid. The method comprises contacting to the nucleic acid a bis-dicationic aryl furan compound, such as 2,5-bis�4-(4,5,6,7-tetrahydro-1H-1,3-diazepin-2-yl) phenyl! furan; 2,5-bis{�4-(N-isopropyl) amidino! phenyl}furan; and physiologically acceptable salts thereof, and exposing the nucleic acid to light at a frequency to induce fluorescence of the compound. A method for fluorescent detection of cytoskeleton elements, and novel bis-dicationic aryl furan compounds are also disclosed.

Abstract translation: 公开了一种荧光检测核酸的方法。 该方法包括使双酸性芳基呋喃化合物如2,5-双[4-（4,5,6,7-四氢-1H-1,3-二氮杂-2-基）苯基 ]呋喃 2,5-双{[4-（N-异丙基）脒基]苯基}呋喃; 和其生理上可接受的盐，并且以一定的频率使核酸暴露以诱导化合物的荧光。 还公开了细胞骨架元件的荧光检测方法，以及新型的双 - 二盐酸芳基呋喃化合物。

公开(公告)号：US5686456A

公开(公告)日：1997-11-11

申请号：US564879

申请日：1995-11-28

Applicant: David W. Boykin ,  Christine C. Dykstra ,  Richard R. Tidwell ,  James E. Hall ,  W. David Wilson ,  Arvind Kumar

Inventor： David W. Boykin ,  Christine C. Dykstra ,  Richard R. Tidwell ,  James E. Hall ,  W. David Wilson ,  Arvind Kumar

IPC: G01N33/50 ,  A61K31/505 ,  A61K31/506 ,  C07D239/26 ,  C07D307/52 ,  C07D307/54 ,  C07D307/58 ,  C07D403/10 ,  C07D403/14 ,  C07D405/14 ,  C09B23/01 ,  C12Q1/68 ,  G01N21/78 ,  G01N33/52 ,  G01N33/58

CPC classification number: C07D239/26 ,  A61K31/505 ,  A61K31/506 ,  C07D307/54 ,  C07D403/10 ,  C07D403/14 ,  C07D405/14 ,  C09B23/0075 ,  G01N33/52

Abstract: The present invention provides methods for treating Pneumocystis carinii pneumonia in a subject in need of such treatment. The methods comprise administering to a subject in need thereof, a pyrimidine of Formula I. ##STR1## wherein the variables are as defined in the specification.

Abstract translation: 本发明提供了在需要这种治疗的个体中治疗卡氏肺囊虫肺炎的方法。 所述方法包括向有需要的受试者施用式I的嘧啶。其中变量如说明书中所定义。

公开(公告)号：US09059243B2

公开(公告)日：2015-06-16

申请号：US13531654

申请日：2012-06-25

Applicant: Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC: H01L21/70 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

Abstract translation: 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

公开(公告)号：US08819857B2

公开(公告)日：2014-08-26

申请号：US13404628

申请日：2012-02-24

Applicant: Naga Gurumoorthy ,  Arvind Kumar ,  Matthew J. Parker

Inventor： Naga Gurumoorthy ,  Arvind Kumar ,  Matthew J. Parker

IPC: G06F11/00

CPC classification number: G06F21/88 ,  G06F9/4401 ,  G06F9/44542 ,  G06F21/575 ,  G06F21/73 ,  G06F2221/2141

Abstract: In some embodiments, a processor-based system may include a processor, the processor having a processor identification, one or more electronic components coupled to the processor, at least one of the electronic components having a component identification, and a hardware security component coupled to the processor and the electronic component. The hardware security component may include a secure non-volatile memory and a controller. The controller may be configured to receive the processor identification from the processor, receive the at least one component identification from the one or more electronic components, and determine if a boot of the processor-based system is a provisioning boot of the processor-based system. If the boot is determined to be the provisioning boot, the controller may be configured to store a security code in the secure non-volatile memory, wherein the security code is based on the processor identification and the at least one component identification. Other embodiments are disclosed and claimed.

Abstract translation: 在一些实施例中，基于处理器的系统可以包括处理器，处理器具有处理器标识，耦合到处理器的一个或多个电子部件，具有部件识别的电子部件中的至少一个以及耦合到 处理器和电子元件。 硬件安全组件可以包括安全的非易失性存储器和控制器。 控制器可以被配置为从处理器接收处理器标识，从一个或多个电子部件接收至少一个组件标识，并且确定基于处理器的系统的启动是否是基于处理器的系统的供应引导 。 如果确定引导是供应启动，则控制器可以被配置为将安全代码存储在安全非易失性存储器中，其中安全代码基于处理器标识和至少一个组件标识。 公开和要求保护其他实施例。

公开(公告)号：US20140075211A1

公开(公告)日：2014-03-13

申请号：US13608479

申请日：2012-09-10

Applicant: Arvind Kumar ,  Brian E. Woodruff ,  David M. Putzolu ,  Mark R. Walker

Inventor： Arvind Kumar ,  Brian E. Woodruff ,  David M. Putzolu ,  Mark R. Walker

IPC: G06F1/26

CPC classification number: G06F1/266 ,  G06F1/3206 ,  G06F1/3234 ,  H04W52/0229 ,  H04W52/0254 ,  Y02D70/164

Abstract: A method and system for cascading power consumption is described herein. The method may include providing power to a first sensor and a second sensor, wherein the first sensor consumes more power than the second sensor. The method may also include detecting the first sensor does not capture a sample of data. In addition, the method may include stopping the flow of power to the first sensor. Furthermore, the method may include monitoring an operating environment with the second sensor. The method may also include providing power to the first sensor in response to the second sensor detecting a sample of data.

Abstract translation: 本文描述了用于级联功率消耗的方法和系统。 该方法可以包括向第一传感器和第二传感器提供电力，其中第一传感器比第二传感器消耗更多的功率。 该方法还可以包括检测第一传感器不捕获数据样本。 此外，该方法可以包括停止向第一传感器的电力的流动。 此外，该方法可以包括利用第二传感器来监视操作环境。 该方法还可以包括响应于第二传感器检测数据样本而向第一传感器提供电力。

公开(公告)号：US20130179693A1

公开(公告)日：2013-07-11

申请号：US13782484

申请日：2013-03-01

Applicant: Ned M. Smith ,  Vedvyas Shanbhogue ,  Arvind Kumar ,  Purushottam Goel

Inventor： Ned M. Smith ,  Vedvyas Shanbhogue ,  Arvind Kumar ,  Purushottam Goel

IPC: G06F21/44

CPC classification number: G06F21/554 ,  G06F21/44 ,  G06F21/57 ,  G06F21/64

Abstract: In one embodiment, a processor includes a microcode storage including processor instructions to create and execute a hidden resource manager (HRM) to execute in a hidden environment that is not visible to system software. The processor may further include an extend register to store security information including a measurement of at least one kernel code module of the hidden environment and a status of a verification of the at least one kernel code module. Other embodiments are described and claimed.