公开(公告)号：US06519689B2

公开(公告)日：2003-02-11

申请号：US09764567

申请日：2001-01-16

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G06F1200

CPC分类号： G06F13/4243

摘要： A method and apparatus for processing pipelined command packets in a packetized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a “read” or a “write”) and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal. Thus, the start command signal is generated after the flag signal by a delay that corresponds to the type of memory command and the clock speed. The latched command bits and the start command signal are applied to a command processor that executes the commands in a pipeline using a sequencer to generate a sequence of timing signals, and generates command signals from the latched command bits. The specific timing signal used is a function of the type of memory operation corresponding to the command bits and the clock speed. The command processor generates and applies an acknowledgment signal to the command unit upon receipt of the start command signal. The command unit is available to receive a new command upon receipt of the acknowledgment signal.

摘要翻译： 一种用于在分组存储器件中处理流水线命令分组的方法和装置。 命令分组最初存储在几个命令单元中的一个中，并且命令随后被耦合到公共命令处理器用于执行。 命令单元各自包括用于存储命令分组的锁存器，计数器和启动命令生成器。 计数器预先加载与在存储器件内的位置接收命令的定时对应的计数。 计数器响应于使用命令包接收到的标志位开始计数。 启动命令发生器接收计数器的计数，并且根据命令的类型（例如，“读取”或“写入”）解码不同的计数以及用于控制命令的操作的时钟信号的速度 存储设备。 当启动命令发生器解码计数时，它锁存所应用的命令包的命令位，并产生起始命令信号。 因此，在标志信号之后产生对应于存储器命令的类型和时钟速度的延迟的起始命令信号。 锁存的命令位和起始命令信号被施加到使用定序器执行流水线中的命令的命令处理器，以产生定时信号序列，并从锁存的命令位产生命令信号。 使用的具体定时信号是对应于命令位和时钟速度的存储器操作的类型的函数。 命令处理器在接收到开始命令信号时产生并向命令单元应用确认信号。 命令单元可以在接收到确认信号时接收新的命令。

公开(公告)号：US06178488B1

公开(公告)日：2001-01-23

申请号：US09141838

申请日：1998-08-27

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G06F1218

CPC分类号： G06F13/4243

摘要： A method and apparatus for processing pipelined command packets in a packefized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a “read” or a “write”) and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal. Thus, the start command signal is generated after the flag signal by a delay that corresponds to the type of memory command and the clock speed. The latched command bits and the start command signal are applied to a command processor that executes the commands in a pipeline using a sequencer to generate a sequence of timing signals, and generates command signals from the latched command bits. The specific timing signal used is a function of the type of memory operation corresponding to the command bits and the clock speed. The command processor generates and applies an acknowledgment signal to the command unit upon receipt of the start command signal. The command unit is available to receive a new command upon receipt of the acknowledgment signal.

摘要翻译： 一种用于在封装的存储器件中处理流水线命令分组的方法和装置。 命令分组最初存储在几个命令单元中的一个中，并且命令随后被耦合到公共命令处理器用于执行。 命令单元各自包括用于存储命令分组的锁存器，计数器和启动命令生成器。 计数器预先加载与在存储器件内的位置接收命令的定时对应的计数。 计数器响应于使用命令包接收到的标志位开始计数。 启动命令发生器接收计数器的计数，并且根据命令的类型（例如，“读取”或“写入”）解码不同的计数以及用于控制命令的操作的时钟信号的速度 存储设备。 当启动命令发生器解码计数时，它锁存所应用的命令包的命令位，并产生起始命令信号。 因此，在标志信号之后产生对应于存储器命令的类型和时钟速度的延迟的起始命令信号。 锁存的命令位和起始命令信号被施加到使用定序器执行流水线中的命令的命令处理器，以产生定时信号序列，并从锁存的命令位产生命令信号。 使用的具体定时信号是对应于命令位和时钟速度的存储器操作的类型的函数。 命令处理器在接收到开始命令信号时产生并向命令单元应用确认信号。 命令单元可以在接收到确认信号时接收新的命令。

公开(公告)号：US06175905B1

公开(公告)日：2001-01-16

申请号：US09126318

申请日：1998-07-30

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G06F1216

CPC分类号： G11C7/109 ,  G11C7/1039 ,  G11C7/1078

摘要： A method and system for bypassing command pipelines in a pipelined memory command generator is used whenever commands must be generated with a latency that is shorter than the latency at which commands can be generated using the command pipelines. The timing of commands issued by the command pipelines is a function of a digital word, and the digital word therefore indicates the latency of the command generator. When the digital word corresponds to a latency that is shorter than the latency at which the command pipeline can generate commands for read and write operations, a bypass circuit—rather than the command pipeline—generates the commands. The bypass circuit is capable of generating the commands with a latency that is shorter than the latency at which the command pipeline is capable of issuing the commands. In addition to issuing the commands, the bypass circuit generates an inhibit signal to prevent the command pipelines from generating duplicate commands.

摘要翻译： 只要命令必须生成的延迟短于使用命令管道生成命令的延迟时间，就可以使用用于绕过流水线存储器命令生成器中的命令管道的方法和系统。 命令管线发出的命令的定时是数字字的函数，因此数字字表示命令发生器的等待时间。 当数字字对应于等待时间短于命令管道可以生成用于读写操作的命令的延迟时，旁路电路而不是命令流水线生成命令。 旁路电路能够以比命令管道能够发出命令的等待时间更短的等待时间生成命令。 除了发出命令之外，旁路电路产生禁止信号，以防止命令管道产生重复命令。

公开(公告)号：US06169331A

公开(公告)日：2001-01-02

申请号：US09143526

申请日：1998-08-28

申请人： Troy A. Manning ,  Michael B. Ball

发明人： Troy A. Manning ,  Michael B. Ball

IPC分类号： H01L23495

CPC分类号： H01L24/85 ,  H01L23/52 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4556 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/48477 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/4911 ,  H01L2224/4917 ,  H01L2224/4942 ,  H01L2224/49426 ,  H01L2224/49429 ,  H01L2224/78301 ,  H01L2224/78313 ,  H01L2224/78318 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85207 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/30105 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A method and apparatus for electrically coupling bond pads on the surface of a microelectronic device. The apparatus can include a microelectronic device having at least two bond pads with a conductive member extending between the bond pads, external to the device. In one embodiment, the conductive member can be connected directly to the bond pads and can extend between the bond pads at or above the surface of the microelectronic device. In another embodiment, the conductive member can be connected on top of another conductive member previously attached to one of the bond pads. The conductive members can be attached to each other or to the bond pads with either ball bonds or wedge bonds to provide electrical signals to selected bond pads of the microelectronic device.

摘要翻译： 一种用于电耦合微电子器件表面上的接合焊盘的方法和装置。 该装置可以包括具有至少两个接合焊盘的微电子器件，该焊盘具有在器件外部的接合焊盘之间延伸的导电部件。 在一个实施例中，导电构件可以直接连接到接合焊盘，并且可以在微电子器件的表面处或上方的接合焊盘之间延伸。 在另一个实施例中，导电构件可以连接在预先连接到一个接合焊盘的另一个导电构件的顶部上。 导电构件可以用球接合或楔形键彼此附接到接合焊盘，以向微电子器件的选定接合焊盘提供电信号。

公开(公告)号：US6014759A

公开(公告)日：2000-01-11

申请号：US874315

申请日：1997-06-13

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G11C29/48 ,  G11C8/00

CPC分类号： G11C29/48

摘要： A memory device includes an output data path that uses single-ended data in conjunction with a flag signal. The output data path transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern if the data does not match the desired pattern outputs the flag signal. The flag signal is input to the output buffer and the output buffer outputs a tri-state condition on the data bus. Since the flag signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.

公开(公告)号：US6002613A

公开(公告)日：1999-12-14

申请号：US966762

申请日：1997-11-10

申请人： Eugene H. Cloud ,  Brett Williams ,  Troy A. Manning

发明人： Eugene H. Cloud ,  Brett Williams ,  Troy A. Manning

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

CPC分类号： G11C7/1063 ,  G11C11/4076 ,  G11C7/1051 ,  G11C7/22

摘要： A memory circuit is described which includes memory cells for storing data. The memory circuit can be read from or written to by an external system such as a microprocessor or core logic chip set. The microprocessor provides memory cell address data to the memory circuit and can request that data be output on communication lines for reading therefrom. The memory circuit reduces the time needed to read data stored in the memory by providing a valid output data signal. The valid output data signal indicates that data coupled to the communication lines has stabilized and is therefore valid. Different valid output data signals and trigger circuits for producing the signals are described.

摘要翻译： 描述了包括用于存储数据的存储单元的存储器电路。 存储器电路可以由诸如微处理器或核心逻辑芯片组的外部系统读取或写入。 微处理器向存储器电路提供存储单元地址数据，并且可以请求在通信线路上输出数据以从中读出数据。 存储器电路通过提供有效的输出数据信号来减少读取存储在存储器中的数据所需的时间。 有效输出数据信号表示耦合到通信线路的数据已经稳定，因此是有效的。 描述了用于产生信号的不同的有效输出数据信号和触发电路。

公开(公告)号：US5996043A

公开(公告)日：1999-11-30

申请号：US874690

申请日：1997-06-13

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G06F12/00

CPC分类号： G11C7/1072

摘要： A command buffer for use in packetized DRAM includes a two stage shift register for shifting for sequentially storing two of the four 10-bit command words in each packet. After the first two words of each packet have been shifted into the shift register, they are transferred to a first storage register and output from the first storage register. After the final two words of each packet have been shifted into the shift register, they are transferred to a second storage register and output from the second storage register. The first two command words are output from the first storage register before the last two command words are applied to the command buffer. As a result, the DRAM can start processing the first two command words of the command packet before the entire command packet has been received. The command buffer also includes circuitry for determining whether a command packet is intended for the memory device containing the command buffer or whether it is intended for another memory device.

摘要翻译： 用于分组化DRAM的命令缓冲器包括两级移位寄存器，用于移位以在每个数据包中顺序存储四个10位命令字中的两个。 在每个分组的前两个字被移入移位寄存器之后，它们被传送到第一个存储寄存器并从第一个存储寄存器输出。 在每个分组的最后两个字已经移入移位寄存器之后，它们被传送到第二存储寄存器并从第二存储寄存器输出。 在将最后两个命令字应用于命令缓冲区之前，从第一存储寄存器输出前两个命令字。 结果，DRAM可以在接收到整个命令分组之前开始处理命令分组的前两个命令字。 命令缓冲器还包括用于确定命令分组是否意图用于包含命令缓冲器的存储器设备或者是否意图用于另一存储器设备的电路。

公开(公告)号：US5946244A

公开(公告)日：1999-08-31

申请号：US811918

申请日：1997-03-05

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G11C7/00 ,  G11C7/22 ,  H03K5/13 ,  H03L7/081

CPC分类号： G11C7/222 ,  G11C7/22 ,  H03K5/131 ,  H03L7/0814

摘要： A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output clock signal that is compared at a race detection circuit to the input clock signal. If the delayed clock signal leads the input clock signal, the race detection circuit increments a counter that controls the binary-coupled capacitors. The incremented counter increases the capacitance by coupling additional capacitance to the variable delay line to delay propagation of the delayed clock signal. If the delayed clock signal lags the original clock signal, the race detection circuit decrements the counter to decrease the capacitance, thereby decreasing the delay of the variable delay line. The race detection circuit includes an arbitration circuit that detects when the delayed clock signal and the variable clock signal are substantially synchronized and disables incrementing or decrementing of the counter in response.

公开(公告)号：US5940608A

公开(公告)日：1999-08-17

申请号：US798226

申请日：1997-02-11

申请人： Troy A. Manning

发明人： Troy A. Manning

IPC分类号： G11C11/407 ,  G06F1/10 ,  H03K5/13 ,  H03L7/093 ,  H03L7/099 ,  G06F1/12

CPC分类号： G06F1/10 ,  H03K5/131

摘要： A clock generator circuit for an integrated circuit includes a phase detector comparing the phase of a delayed external clock signal to the phase of an internal clock signal. An error signal corresponding to the difference in phase between the two clock signals is applied to a differential amplifier where the error signal is offset by a value corresponding to the delay of an external clock signal as it is coupled to the phase detector. The offset error signal is applied to a control input of a voltage controlled oscillator which generates the internal clock signal. The phase of the internal clock signal it thus adjusted so that it is substantially the same as the phase of the external clock signal before being delayed as it is coupled to the phase detector and other circuitry in the integrated circuit. The voltage controlled oscillator is constructed to operate in a plurality of discrete frequency bands so that the offset error signal need only control the frequency of the internal clock signal over a relatively small range. The frequency band is selected by a signal from a register that is programmed by a user with data identifying the frequency of the external clock signal.

公开(公告)号：US5936428A

公开(公告)日：1999-08-10

申请号：US146304

申请日：1998-09-03

申请人： Todd A. Merritt ,  Troy A. Manning

发明人： Todd A. Merritt ,  Troy A. Manning

IPC分类号： H03K3/356 ,  H03K19/0185

CPC分类号： H03K3/356113 ,  H03K3/356017

摘要： A voltage level translator is disclosed which translates a CMOS input signal into a CMOS output signal where the low voltage level of the output signal is equal to the high voltage level of the input signal. The voltage level translator is described in an integrated circuit such as memory circuits, including DRAMs. Specifically, the voltage level translator produces an output signal which can be used as a gate voltage on a precharge transistor for a booted circuit where the gate voltage need only drop to the high voltage level of the input signal to shut the transistor off. The voltage level translator described, therefore, reduces the time and power required to translate an input signal by limiting the voltage swing of the output signal.

摘要翻译： 公开了一种电压电平转换器，其将CMOS输入信号转换成CMOS输出信号，其中输出信号的低电压电平等于输入信号的高电压电平。 在诸如包括DRAM的存储器电路的集成电路中描述了电压电平转换器。 具体地，电压电平转换器产生一个输出信号，该输出信号可以用作用于引导电路的预充电晶体管上的栅极电压，其中栅极电压只需要下降到输入信号的高电压电平以关闭晶体管。 因此，所描述的电压电平转换器通过限制输出信号的电压摆幅来减少转换输入信号所需的时间和功率。