公开(公告)号：US20170229359A1

公开(公告)日：2017-08-10

申请号：US15494501

申请日：2017-04-22

申请人： Renesas Electronics Corporation

发明人： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC分类号： H01L21/66 ,  H01L23/00

CPC分类号： H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

公开(公告)号：US09646901B2

公开(公告)日：2017-05-09

申请号：US15219254

申请日：2016-07-25

申请人： Renesas Electronics Corporation

发明人： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC分类号： H01L23/58 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  G01R31/26

CPC分类号： H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

公开(公告)号：US09281457B2

公开(公告)日：2016-03-08

申请号：US13910245

申请日：2013-06-05

申请人： Nichia Corporation

发明人： Satoshi Shirahama

IPC分类号： H01L21/44 ,  H01L21/00 ,  H01L33/52 ,  H01L23/495 ,  H01L23/00 ,  H01L33/62

CPC分类号： H01L33/52 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L33/62 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/4809 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/20751 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20752 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/4554

摘要： Provided is a semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device has a semiconductor element having a plurality of wires bonded to the semiconductor element with sufficient bonding reliability and has a good heat dissipation property. A semiconductor device in which a first wire is ball bonded on an electrode, and a second wire is further bonded on the ball-bonded first wire, and the first wire or an end of the second wire defines a space between itself and the ball portion of the first wire.

公开(公告)号：US20150214451A1

公开(公告)日：2015-07-30

申请号：US14421138

申请日：2013-09-04

申请人： PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

发明人： Masumi Abe ,  Yasufumi Wada ,  Toshifumi Ogata ,  Kenji Sugiura

IPC分类号： H01L33/62 ,  F21S4/00 ,  F21V23/00 ,  H01L33/54

CPC分类号： H01L33/62 ,  F21S4/28 ,  F21V23/003 ,  F21V23/005 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0753 ,  H01L33/54 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/4945 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45014 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Each of a plurality of semiconductor light-emitting element has, on an upper surface thereof that has a quadrilateral shape, a pair of connecting portions having different polarities from each other. The pair of connecting portions are aligned on a diagonal of the quadrilateral shape. The diagonal intersects a row direction along which the semiconductor light-emitting elements within a row are arranged. Connecting portions having identical polarity are positioned on an imaginary line parallel to the row direction. Metal wires intersect two sides extending from a corner, on the diagonal, of the upper surface of each of the semiconductor light-emitting elements when viewed from a direction perpendicular to a mounting surface of a substrate for mounting the semiconductor light-emitting elements.

摘要翻译： 多个半导体发光元件中的每一个在具有四边形形状的上表面上具有彼此不同极性的一对连接部。 该对连接部分在四边形形状的对角线上对齐。 该对角线与排列有一排的半导体发光元件的行方向交叉。 具有相同极性的连接部分位于平行于行方向的假想线上。 当从垂直于用于安装半导体发光元件的基板的安装表面的方向观察时，金属线从每个半导体发光元件的上表面的对角线的角部延伸的两侧相交。

公开(公告)号：US08912540B2

公开(公告)日：2014-12-16

申请号：US13802704

申请日：2013-03-13

申请人： Renesas Electronics Corporation

发明人： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

摘要翻译： 提供了一种在半导体芯片上具有焊盘的半导体器件，形成在半导体芯片上并且在探针区域的焊盘上的开口部分和耦合区域的第一钝化膜，形成在焊盘上的第二钝化膜和第一钝化膜 钝化膜并且在耦合区域的焊盘上具有开口部分，以及重新布线层，形成在耦合区域和第二钝化膜上并电耦合到焊盘。 相对于耦合区域放置在半导体芯片的周边侧的探针区域的焊盘具有探针标记，并且重新布线层从半导体芯片的耦合区域延伸到中心侧。 本发明提供能够实现半导体器件的尺寸减小，特别是间距变窄的技术。

公开(公告)号：US20140361299A1

公开(公告)日：2014-12-11

申请号：US14465975

申请日：2014-08-22

申请人： Renesas Electronics Corporation

发明人： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

摘要翻译： 提供了一种在半导体芯片上具有焊盘的半导体器件，形成在半导体芯片上并且在探针区域的焊盘上的开口部分和耦合区域的第一钝化膜，形成在焊盘上的第二钝化膜和第一钝化膜 钝化膜并且在耦合区域的焊盘上具有开口部分，以及重新布线层，形成在耦合区域和第二钝化膜上并电耦合到焊盘。 相对于耦合区域放置在半导体芯片的周边侧的探针区域的焊盘具有探针标记，并且重新布线层从半导体芯片的耦合区域延伸到中心侧。 本发明提供能够实现半导体器件的尺寸减小，特别是间距变窄的技术。

公开(公告)号：US08604627B2

公开(公告)日：2013-12-10

申请号：US11918407

申请日：2006-04-14

申请人： Hideki Hiromoto ,  Sadamasa Fujii ,  Tsunemori Yamaguchi

发明人： Hideki Hiromoto ,  Sadamasa Fujii ,  Tsunemori Yamaguchi

IPC分类号： H01L23/49

CPC分类号： H01L24/85 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49517 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/4848 ,  H01L2224/48997 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/48455 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： The present invention aims at providing a semiconductor device capable of reliably preventing a wire bonded to an island from being disconnected due to a thermal shock, a temperature cycle and the like in mounting and capable of preventing remarkable increase in the process time. In the semiconductor device according to the present invention, a semiconductor chip is die-bonded to the surface of an island, one end of a first wire is wire-bonded to an electrode formed on the surface of the semiconductor chip to form a first bonding section and the other end of the first wire is wire-bonded to the island to form a second bonding section, while the semiconductor device is resin-sealed. A double bonding section formed by wire-bonding a second wire is provided on the second bonding section of the first wire wire-bonded onto the island.

摘要翻译： 本发明的目的在于提供一种能够可靠地防止由于安装时的热冲击，温度循环等而使与岛部接合的引线断线的半导体装置，能够防止显着增加处理时间。 在根据本发明的半导体器件中，半导体芯片被芯片接合到岛的表面，第一线的一端被引线接合到形成在半导体芯片的表面上的电极，以形成第一接合 并且第一线的另一端被引线接合到岛以形成第二接合部，同时半导体器件被树脂密封。 在第一导线接合到岛上的第二接合部上设置有通过引线接合第二线形成的双接合部。

公开(公告)号：US20130292834A1

公开(公告)日：2013-11-07

申请号：US13853268

申请日：2013-03-29

申请人： TESSERA, INC.

发明人： Belgacem Haba ,  Philip Damberg ,  Philip R. Osborn

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/49816 ,  H01L21/50 ,  H01L23/13 ,  H01L23/49861 ,  H01L24/01 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/40091 ,  H01L2224/40225 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/4813 ,  H01L2224/4824 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/48477 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/49112 ,  H01L2224/4942 ,  H01L2224/49427 ,  H01L2224/49429 ,  H01L2224/4945 ,  H01L2224/85051 ,  H01L2224/85191 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19107 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48095 ,  H01L2224/37099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： First and second bond elements, e.g., wire bonds, electrically connect a chip contact with one or more substrate contacts of a substrate, and can be arranged so that the second bond element is joined to the first bond element at each end and so that the second bond element does not touch the chip contact or one or more substrate contacts. A third bond element can be joined to ends of the first and second bond elements. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact.

摘要翻译： 第一和第二接合元件，例如引线键合，将芯片接触件与衬底的一个或多个衬底触点电连接，并且可以被布置成使得第二接合元件在每个端部与第一接合元件接合， 第二接合元件不接触芯片接触或一个或多个衬底触点。 第三接合元件可以连接到第一和第二接合元件的端部。 在一个实施例中，接合元件可以具有环形连接，其具有在第一接触处连接的第一端和第二端以及与第二接触连接的中间部。

公开(公告)号：US20130267050A1

公开(公告)日：2013-10-10

申请号：US13910245

申请日：2013-06-05

申请人： Nichia Corporation

发明人： Satoshi SHIRAHAMA

IPC分类号： H01L33/52

CPC分类号： H01L33/52 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L33/62 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/4809 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/20751 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20752 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/4554

摘要： Provided is a semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device has a semiconductor element having a plurality of wires bonded to the semiconductor element with sufficient bonding reliability and has a good heat dissipation property. A semiconductor device in which a first wire is ball bonded on an electrode, and a second wire is further bonded on the ball-bonded first wire, and the first wire or an end of the second wire defines a space between itself and the ball portion of the first wire.

摘要翻译： 本发明提供一种半导体装置及半导体装置的制造方法，其中半导体装置具有半导体元件，该半导体元件具有多个导线，该多个导线以足够的接合可靠性与半导体元件结合，并具有良好的散热性能。 一种半导体器件，其中第一线被球接在电极上，并且第二线还被接合在球形接合的第一线上，并且第一线或第二线的端部在其自身和球部之间限定空间 的第一根线。

公开(公告)号：US20130193438A1

公开(公告)日：2013-08-01

申请号：US13802704

申请日：2013-03-13

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Toshihiko Akiba ,  Bunji Yusumura ,  Masanao Sato ,  Hiromi Abe

IPC分类号： H01L21/66

CPC分类号： H01L22/32 ,  G01R31/26 ,  H01L22/14 ,  H01L22/20 ,  H01L22/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/4911 ,  H01L2224/49429 ,  H01L2224/49431 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85951 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

摘要： Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

摘要翻译： 提供了一种在半导体芯片上具有焊盘的半导体器件，形成在半导体芯片上并且在探针区域的焊盘上的开口部分和耦合区域的第一钝化膜，形成在焊盘上的第二钝化膜和第一钝化膜 钝化膜并且在耦合区域的焊盘上具有开口部分，以及重新布线层，形成在耦合区域和第二钝化膜上并电耦合到焊盘。 相对于耦合区域放置在半导体芯片的周边侧的探针区域的焊盘具有探针标记，并且重新布线层从半导体芯片的耦合区域延伸到中心侧。 本发明提供能够实现半导体器件的尺寸减小，特别是间距变窄的技术。