公开(公告)号：US20050266652A1

公开(公告)日：2005-12-01

申请号：US10709768

申请日：2004-05-27

申请人： Michael Chudzik ,  Louis Hsu ,  Joseph Shepard ,  William Tonti

发明人： Michael Chudzik ,  Louis Hsu ,  Joseph Shepard ,  William Tonti

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L23/522

CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L23/5227 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.

摘要翻译： 用于利用垂直交错电极的结构，装置和方法用于增加电容器面积，同时保持最小的水平脚印。 由于电容与表面积成比例，因此该结构能够连续使用当前厚度的当前介电材料，例如Si 3 N 4。 在叉指MIMCAP结构的第二实施例中，电极以螺旋方式形成，其用于增加MIMCAP的物理强度。 还包括螺旋形电容器电极，其通过提供电路设计者容易指定的宽范围的离散电容值来适应模块化设计。

公开(公告)号：US20050188289A1

公开(公告)日：2005-08-25

申请号：US10708316

申请日：2004-02-24

申请人： Zachary Berndlmaier ,  Stephen Geissler ,  William Tonti

发明人： Zachary Berndlmaier ,  Stephen Geissler ,  William Tonti

IPC分类号： G01R31/28 ,  G01R31/317

CPC分类号： G01R31/31718 ,  G01R31/31707

摘要： Disclosed is a method and apparatus for autonomously self-monitoring and self-adjusting the operation of an integrated circuit device throughout the integrated circuit device's useful life. The invention periodically performs performance self-testing on the integrated circuit device throughout the integrated circuit devices useful life. The invention also evaluates whether results from the self-testing are within acceptable limits and self-adjusts parameters of the integrated circuit device until the results from the self-testing are within the acceptable limits.

摘要翻译： 公开了一种在整个集成电路器件的使用寿命内自主地自我监测和自调整集成电路器件的操作的方法和装置。 本发明在整个集成电路器件的使用寿命中定期对集成电路器件进行性能自检。 本发明还评估自测试的结果是否在可接受的限度内，并且自调整集成电路器件的参数，直到自测试的结果在可接受的限度内。

公开(公告)号：US20050184359A1

公开(公告)日：2005-08-25

申请号：US10708340

申请日：2004-02-25

申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

IPC分类号： H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

摘要翻译： 提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积 下表面。 双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。 在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

公开(公告)号：US20050145983A1

公开(公告)日：2005-07-07

申请号：US11055106

申请日：2005-02-11

申请人： Claude Bertin ,  Ramachandra Divakaruni ,  Russell Houghton ,  Jack Mandelman ,  William Tonti

发明人： Claude Bertin ,  Ramachandra Divakaruni ,  Russell Houghton ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L21/82 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L27/10829 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

公开(公告)号：US20050144524A1

公开(公告)日：2005-06-30

申请号：US10863194

申请日：2004-06-08

申请人： Anthony Bonaccio ,  Michael LeStrange ,  William Tonti ,  Sebastian Ventrone

发明人： Anthony Bonaccio ,  Michael LeStrange ,  William Tonti ,  Sebastian Ventrone

IPC分类号： G06F1/04 ,  G06F11/00

CPC分类号： G06F1/04

摘要： A method a circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter adapted to count pulses of a pulsed signal, the repair processor adapted to (a) replace the original circuit with a first redundant circuit or (b) adapted to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of predetermined cycle counts.

摘要翻译： 一种用于防止集成电路中的故障的电路的方法。 电路包括：原电路; 一个或多个冗余电路; 以及修复处理器，包括适于计数脉冲信号的脉冲的时钟周期计数器，所述修复处理器适于（a）用第一冗余电路替换原始电路，或（b）适于选择另一个冗余电路， 从第二冗余电路到最后一个冗余电路的序列，并且每次循环计数器达到一组预定循环计数的预定计数时，用选定的冗余电路替换先前选择的冗余电路。

公开(公告)号：US06266272B1

公开(公告)日：2001-07-24

申请号：US09364841

申请日：1999-07-30

申请人： Toshiaki Kirihata ,  Daniel Storaska ,  Chandrasekhar Narayan ,  William Tonti ,  Claude Bertin ,  Nick van Heel

发明人： Toshiaki Kirihata ,  Daniel Storaska ,  Chandrasekhar Narayan ,  William Tonti ,  Claude Bertin ,  Nick van Heel

IPC分类号： G11C1450

CPC分类号： G11C16/02 ,  G11C11/005

摘要： A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.

摘要翻译： 部分非易失性动态随机存取存储器（PNDRAM）使用由多个单晶体管（1T）单元或两个晶体管（2T）单元形成的DRAM阵列。 电池可电可编程为非易失性存储器。 这导致具有动态随机存取存储器（DRAM）和电可编程只读存储器（EPROM）的单芯片设计。 集成在PNDRAM中的DRAM和EPROM可以随时重新配置，无论是在制造还是在现场。 PNDRAM具有多个应用，例如将主内存与ID，BIOS或操作系统信息组合在一个芯片中。