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    SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES
    2.
    发明申请
    SEMICONDUCTOR STRUCTURES INTEGRATING DAMASCENE-BODY FINFET'S AND PLANAR DEVICES ON A COMMON SUBSTRATE AND METHODS FOR FORMING SUCH SEMICONDUCTOR STRUCTURES 有权
    在公共基板上集成大面积金属体和平面器件的半导体结构及其形成这样的半导体结构的方法

    公开(公告)号：US20080050866A1

    公开(公告)日：2008-02-28

    申请号：US11927780

    申请日：2007-10-30

    申请人： Roger Booth ,  Jack Mandelman ,  William Tonti

    发明人： Roger Booth ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L21/336

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

    摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

    摘要翻译： 通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。

    E-Fuse and Method for Fabricating E-Fuses Integrating Polysilicon Resistor Masks
    3.
    发明申请
    E-Fuse and Method for Fabricating E-Fuses Integrating Polysilicon Resistor Masks 审中-公开
    电子保险丝和电子熔丝的制造方法，集成多晶硅电阻掩模

    公开(公告)号：US20080029843A1

    公开(公告)日：2008-02-07

    申请号：US11873197

    申请日：2007-10-16

    申请人： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

    发明人： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/41

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An E-fuse and a method for fabricating an E-fuse integrating polysilicon resistor masks, and a design structure on which the subject E-fuse circuit resides are provided. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.

    摘要翻译： 一种电熔丝和一种用于制造集成多晶硅电阻掩模的电子熔丝的方法，以及设置有被检体E熔丝回路的设计结构。 电熔丝包括限定熔丝形状的多晶硅层，其包括阴极，阳极和连接在阴极和阳极硅化物层之间的保险丝颈。 硅化物形成在多晶硅层上形成，其中非硅化部分在靠近熔丝颈部的阴极的一部分上延伸。 非接触部分基本上防止电流在阴极的硅化物形成区域中流动，在保险丝编程期间在保险丝颈部发生电迁移。 非接触部分具有比熔丝颈部的串联电阻显着更低的串联电阻。

    Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof
    4.
    发明申请
    Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof 失效
    具有位于不同高度的端子部分的电可编程熔丝结构及其制造方法

    公开(公告)号：US20070210411A1

    公开(公告)日：2007-09-13

    申请号：US11372334

    申请日：2006-03-09

    申请人： William Hovis ,  Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

    发明人： William Hovis ,  Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

    IPC分类号： H01L21/82 ,  H01L29/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.

    摘要翻译： 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处，并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。 第一端子部分和第二端子部分平行于支撑表面定向，而熔丝元件包括垂直于支撑表面定向的部分，并且包括至少一个直角弯曲部，其从第一和第二端子部分中的至少一个过渡到 保险丝元件的正交取向部分。

    Programmable anti-fuse structures, methods for fabricating programmable anti-fuse structures, and methods of programming anti-fuse structures
    5.
    发明申请
    Programmable anti-fuse structures, methods for fabricating programmable anti-fuse structures, and methods of programming anti-fuse structures 审中-公开
    可编程反熔丝结构，制造可编程反熔丝结构的方法以及编程反熔丝结构的方法

    公开(公告)号：US20070205485A1

    公开(公告)日：2007-09-06

    申请号：US11366879

    申请日：2006-03-02

    申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

    发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

    IPC分类号： H01L29/00

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Programmable anti-fuse structures for semiconductor device constructions, fabrication methods for forming anti-fuse structures during semiconductor device fabrication, and programming methods for anti-fuse structures. The programmable anti-fuse structure comprises first and second terminals and an anti-fuse layer electrically coupled with the first and second terminals. An electrically-conductive diffusion layer is disposed between the first terminal and the anti-fuse layer. The diffusion layer inhibits diffusion of conductive material from the first terminal to the anti-fuse layer when the anti-fuse structure is unprogrammed, but permits diffusion of the conductive material when a programming voltage is applied between the first and second terminals during operation. Advantageously, the first terminal may be composed of metal and the anti-fuse layer may be composed of a semiconductor. The methods of fabricating the anti-fuse structure do not require an additional lithographic mask but instead rely on damascene process steps used to fabricate interconnection structures for neighboring active devices.

    摘要翻译： 用于半导体器件结构的可编程抗熔丝结构，在半导体器件制造期间形成抗熔丝结构的制造方法以及用于抗熔丝结构的编程方法。 可编程反熔丝结构包括第一和第二端子以及与第一和第二端子电耦合的抗熔丝层。 导电扩散层设置在第一端子和反熔丝层之间。 当反熔丝结构未编程时，扩散层抑制导电材料从第一端子到抗熔丝层的扩散，但是当在操作期间在第一和第二端子之间施加编程电压时允许导电材料的扩散。 有利地，第一端子可以由金属构成，并且抗熔丝层可以由半导体构成。 制造抗熔丝结构的方法不需要额外的光刻掩模，而是依赖用于制造相邻有源器件的互连结构的镶嵌工艺步骤。

    Memory elements and methods of using the same
    6.
    发明申请
    Memory elements and methods of using the same 失效
    内存元素和使用方法

    公开(公告)号：US20070189076A1

    公开(公告)日：2007-08-16

    申请号：US11353493

    申请日：2006-02-14

    申请人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

    发明人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0466

    摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.

    摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。 控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由 存储元件在第一模式下操作。 提供了许多其他方面。

    Patterned Silicon-on-Insulator layers and methods for forming the same
    8.
    发明申请
    Patterned Silicon-on-Insulator layers and methods for forming the same 失效
    图案化的绝缘体上层及其形成方法

    公开(公告)号：US20060286779A1

    公开(公告)日：2006-12-21

    申请号：US11155029

    申请日：2005-06-16

    申请人： Roger Booth ,  Louis Hsu ,  Jack Mandelman ,  William Tonti

    发明人： Roger Booth ,  Louis Hsu ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L21/76 ,  H01L21/00

    CPC分类号： H01L21/76243

    摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.

    摘要翻译： 在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。 该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。 提供了许多其他方面。

    Storage Elements with Disguised Configurations and Methods of Using the Same
    10.
    发明申请
    Storage Elements with Disguised Configurations and Methods of Using the Same 审中-公开
    具有伪装配置的存储元件及其使用方法

    公开(公告)号：US20080067608A1

    公开(公告)日：2008-03-20

    申请号：US11928663

    申请日：2007-10-30

    申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

    发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

    IPC分类号： H01L27/06

    CPC分类号： H01L23/585 ,  H01L23/5256 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a gate region of the MOSFET; and (3) an implanted region coupled to the source/drain diffusion regions of the MOSFET such that a path between the source/drain diffusion regions functions as a short circuit or an open circuit. In another aspect, a design structure embodied in a machine readable medium for designing manufacturing, or testing a design is provided. Numerous other aspects are provided.

    摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是具有（1）具有源极/漏极扩散区域的金属氧化物半导体场效应晶体管（MOSFET）的集成电路（IC）的元件; （2）耦合到所述MOSFET的电熔丝（eFuse），使得所述eFuse的一部分用作所述MOSFET的栅极区域; 和（3）耦合到MOSFET的源极/漏极扩散区域的注入区域，使得源极/漏极扩散区域之间的路径用作短路或开路。 在另一方面，提供了体现在用于设计制造的机器可读介质或测试设计中的设计结构。 提供了许多其他方面。