公开(公告)号：US08597976B2

公开(公告)日：2013-12-03

申请号：US12683007

申请日：2010-01-06

申请人： ChiaHua Ho ,  Erh-Kun Lai

发明人： ChiaHua Ho ,  Erh-Kun Lai

IPC分类号： H01L21/00 ,  H01L21/16

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1633

摘要： The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.

摘要翻译： 本发明提供具有多个存储层结构的多电平单元存储器结构，其中每个存储层结构包括为多个逻辑状态定义不同读取电流电平的氧化钨区域。 每个存储器层结构可以通过使用提供多电平单元功能的氧化钨区域来提供构成四个逻辑状态的两位信息，其中四个逻辑状态等于四个不同的读取电流电平。 具有两个存储器层结构的存储器结构将提供四位存储位置和16个逻辑状态。 在一个实施例中，第一和第二存储层结构中的每一个包括延伸到钨插塞构件的主表面中的钨氧化物区域，其中钨插塞的外表面被阻挡构件包围。

公开(公告)号：US08461564B2

公开(公告)日：2013-06-11

申请号：US12855630

申请日：2010-08-12

申请人： ChiaHua Ho ,  Erh-Kun Lai

发明人： ChiaHua Ho ,  Erh-Kun Lai

IPC分类号： H01L47/00

CPC分类号： H01L45/1683 ,  B82Y10/00 ,  G11C11/14 ,  G11C11/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

摘要： Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.

摘要翻译： 描述了基于氧化钨存储区域的存储器件以及用于制造的方法以及用于编程这种器件的方法。 在一些实施例中，氧化钨存储区可以通过使用非关键掩模氧化钨材料或甚至根本不进行掩模来形成。 本文描述的存储器件包括底部电极和底部电极上的存储元件。 存储元件包括至少一种钨 - 氧化合物，并且可编程为至少两个电阻状态。 包含阻挡材料的顶部电极在存储元件上，阻挡材料防止金属离子从顶部电极移动到存储元件中。

公开(公告)号：US20100301330A1

公开(公告)日：2010-12-02

申请号：US12855630

申请日：2010-08-12

申请人： ChiaHua Ho ,  Erh-Kun Lai

发明人： ChiaHua Ho ,  Erh-Kun Lai

IPC分类号： H01L29/68

CPC分类号： H01L45/1683 ,  B82Y10/00 ,  G11C11/14 ,  G11C11/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

摘要： Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.

摘要翻译： 描述了基于氧化钨存储区域的存储器件以及用于制造的方法以及用于编程这种器件的方法。 在一些实施例中，氧化钨存储区可以通过使用非关键掩模氧化钨材料或甚至根本不进行掩模来形成。 本文描述的存储器件包括底部电极和底部电极上的存储元件。 存储元件包括至少一种钨 - 氧化合物，并且可编程为至少两个电阻状态。 包含阻挡材料的顶部电极在存储元件上，阻挡材料防止金属离子从顶部电极移动到存储元件中。

公开(公告)号：US20080304312A1

公开(公告)日：2008-12-11

申请号：US11955137

申请日：2007-12-12

申请人： ChiaHua Ho ,  Erh-Kun Lai

发明人： ChiaHua Ho ,  Erh-Kun Lai

IPC分类号： G11C11/00 ,  H05H1/24

CPC分类号： H01L45/1683 ,  B82Y10/00 ,  G11C11/14 ,  G11C11/22 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

摘要： Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.

摘要翻译： 描述了基于氧化钨存储区域的存储器件以及用于制造的方法以及用于编程这种器件的方法。 在一些实施例中，氧化钨存储区可以通过使用非关键掩模氧化钨材料或甚至根本不进行掩模来形成。 本文描述的存储器件包括底部电极和底部电极上的存储元件。 存储元件包括至少一种钨 - 氧化合物，并且可编程为至少两个电阻状态。 包含阻挡材料的顶部电极在存储元件上，阻挡材料防止金属离子从顶部电极移动到存储元件中。

公开(公告)号：US20070241371A1

公开(公告)日：2007-10-18

申请号：US11279945

申请日：2006-04-17

申请人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang Hsieh

发明人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang Hsieh

IPC分类号： H01L29/772 ,  H01L21/8239

CPC分类号： H01L45/1226 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： A memory device includes first and second electrodes separated by an insulating member comprising upwardly and inwardly tapering surfaces connected by a surface segment. A bridge, comprising memory material, such as a phase change material, switchable between electrical property states by the application of energy, is positioned across the surface segment and in contact with the electrodes to define an inter-electrode path defined at least in part by the length of the surface segment. According to a method for making a memory cell device, the tapering surfaces may be created by depositing a dielectric material cap using a high density plasma (HDP) deposition procedure. The electrodes and the dielectric material cap may he planarized to create the surface segment on the dielectric material. At least one of the dielectric material depositing step and the planarizing step may be controlled so that the length of the surface and segment is within a chosen dimensional range, such as between 10 nm and 100 nm.

摘要翻译： 存储器件包括由绝缘构件隔开的第一和第二电极，包括由表面段连接的向上和向内的渐缩表面。 包括可通过施加能量在电性能状态之间切换的记忆材料（例如相变材料）的桥被定位在表面段上并与电极接触以限定至少部分地由 表面段的长度。 根据制造存储单元器件的方法，可以通过使用高密度等离子体（HDP）沉积程序沉积介电材料盖而产生锥形表面。 电极和电介质材料盖可以被平坦化以在电介质材料上产生表面段。 可以控制介电材料沉积步骤和平坦化步骤中的至少一个，使得表面和段的长度在选定的尺寸范围内，例如在10nm和100nm之间。

公开(公告)号：US20080285330A1

公开(公告)日：2008-11-20

申请号：US12134117

申请日：2008-06-05

申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsien

发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsien

IPC分类号： G11C7/00 ,  G11C11/00

CPC分类号： G11C17/165 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0069 ,  G11C17/16 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/77

摘要： A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f) R. The logic “1” state is represented by a mathematical expression (n+f) R. The logic “2” state is represented by a mathematical expression (1+nf) R. The logic “3” state is represented by a mathematical expression n(1+f) R.

摘要翻译： 描述了一种用于操作具有串联排列的两个存储层堆叠的双稳态电阻随机存取存储器的方法。 双稳态电阻随机存取存储器包括每个存储单元的两个存储层堆栈，双稳态电阻随机存取存储器以四个逻辑状态，逻辑“00”状态，逻辑“01”状态，逻辑“10”状态和逻辑 “11”状态。 逻辑“0”状态由数学表达式（1 + f）R表示。逻辑“1”状态为 由数学表达式（n + f）R表示。逻辑“2”状态由数学表达式（1 + nf）R表示。逻辑“3”状态由数学表达式n（1 + f）R 。

公开(公告)号：US20080173931A1

公开(公告)日：2008-07-24

申请号：US11625216

申请日：2007-01-19

申请人： ChiaHua Ho ,  Erh-Kun Lai

发明人： ChiaHua Ho ,  Erh-Kun Lai

IPC分类号： H01L27/00 ,  H01L21/44

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1633

摘要： The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.

摘要翻译： 本发明提供具有多个存储层结构的多电平单元存储器结构，其中每个存储层结构包括为多个逻辑状态定义不同读取电流电平的氧化钨区域。 每个存储器层结构可以通过使用提供多电平单元功能的氧化钨区域来提供构成四个逻辑状态的两位信息，其中四个逻辑状态等于四个不同的读取电流电平。 具有两个存储器层结构的存储器结构将提供四位存储位置和16个逻辑状态。 在一个实施例中，第一和第二存储层结构中的每一个包括延伸到钨插塞构件的主表面中的钨氧化物区域，其中钨插塞的外表面被阻挡构件包围。

公开(公告)号：US20070262388A1

公开(公告)日：2007-11-15

申请号：US11382422

申请日：2006-05-09

申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Hsieh

发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Hsieh

IPC分类号： H01L23/62 ,  H01L21/338

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second electrode is located within an interior of the circumferential extending shape and separated from the first electrode by an insulating material. A resistance memory bridge is in contact with an edge surface of the first and second electrodes. The first electrode in the contact structure is connected to a transistor and the second electrode in the contact structure is connected to a bit line. A bit line is connected to the second electrode by a self-aligning process.

摘要翻译： 公开了一种桥结构中的电阻随机存取存储器，其包括其中第一和第二电极位于接触结构内的接触结构。 第一电极具有围绕接触结构的内壁的周向延伸形状，例如环形形状。 第二电极位于周向延伸形状的内部，并通过绝缘材料与第一电​​极分离。 电阻记忆桥与第一和第二电极的边缘表面接触。 接触结构中的第一电极连接到晶体管，并且接触结构中的第二电极连接到位线。 位线通过自对准工艺连接到第二电极。

公开(公告)号：US07667220B2

公开(公告)日：2010-02-23

申请号：US11625216

申请日：2007-01-19

申请人： ChiaHua Ho ,  Erh-Kun Lai

发明人： ChiaHua Ho ,  Erh-Kun Lai

IPC分类号： H01L47/00

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1633

摘要： The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.

摘要翻译： 本发明提供具有多个存储层结构的多电平单元存储器结构，其中每个存储层结构包括为多个逻辑状态定义不同读取电流电平的氧化钨区域。 每个存储器层结构可以通过使用提供多电平单元功能的氧化钨区域来提供构成四个逻辑状态的两位信息，其中四个逻辑状态等于四个不同的读取电流电平。 具有两个存储器层结构的存储器结构将提供四位存储位置和16个逻辑状态。 在一个实施例中，第一和第二存储层结构中的每一个包括延伸到钨插塞构件的主表面中的钨氧化物区域，其中钨插塞的外表面被阻挡构件包围。

公开(公告)号：US20070201276A1

公开(公告)日：2007-08-30

申请号：US11352788

申请日：2006-02-13

申请人： ChiaHua Ho ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Kuang Hsieh

发明人： ChiaHua Ho ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Kuang Hsieh

IPC分类号： G11C16/04 ,  H01L21/336 ,  G11C11/34 ,  H01L29/788

CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

摘要： Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.

摘要翻译： 存储单元，其包括具有由沟道区域分离的源极区域和漏极区域的半导体衬底; 电荷捕获结构，设置在所述半导体衬底的沟道区之上; 设置在电荷捕获结构上方并靠近源极区的第一栅极; 以及第二栅极，其设置在所述电荷捕获结构的上方并且靠近所述漏极区; 提供了第一栅极和第二栅极被第一纳米级分隔开的区域，以及包括多个这样的电池的阵列，制造这种电池的方法以及操作这种电池的方法。