公开(公告)号：US20180040374A1

公开(公告)日：2018-02-08

申请号：US15228559

申请日：2016-08-04

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Le Zheng ,  Brent Buchanan ,  John Paul Strachan

IPC: G11C15/04

CPC classification number: G11C15/046

Abstract: An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor.

公开(公告)号：US20170323677A1

公开(公告)日：2017-11-09

申请号：US15522344

申请日：2014-10-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ning Ge ,  John Paul Strachan ,  Jianhua Yang ,  Miao Hu

IPC: G11C11/24 ,  G06G7/16 ,  G11C11/34

CPC classification number: G11C11/24 ,  G06G7/16 ,  G11C11/34

Abstract: A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.

公开(公告)号：US09721661B1

公开(公告)日：2017-08-01

申请号：US15216011

申请日：2016-07-21

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  Le Zheng ,  John Paul Strachan

IPC: G11C15/04

CPC classification number: G11C15/046 ,  G11C13/0002 ,  G11C13/0007 ,  G11C15/04

Abstract: An example content addressable memory. A bit cell of the memory may include a memristor and a switching transistor that are connected in series between a first data line and a second data line. The bit cell may also include a match-line transistor connected between a match line and a rail. A gate of the match-line transistor may be connected to a common node of the memristor and the switching transistor. The switching transistor may be sized such that its channel resistance when on is between a resistance associated with a low-resistance state of the memristor and a resistance associated with a high-resistance state of the memristor.

公开(公告)号：US20170178725A1

公开(公告)日：2017-06-22

申请号：US15325543

申请日：2014-10-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jianhua Yang ,  Miao Hu ,  John Paul Strachan ,  Ning Ge

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G06F3/03 ,  G06G7/16 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/0064 ,  G11C2213/79

Abstract: A memristive dot-product system for vector processing is described. The memristive dot-product system includes a crossbar array having a number of memory elements. Each memory element includes a memristor. Each memory element includes a transistor. The system also includes a vector input register. The system also includes a vector output register.

公开(公告)号：US11983604B2

公开(公告)日：2024-05-14

申请号：US17378650

申请日：2021-07-16

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Suhas Kumar ,  John Paul Strachan ,  Thomas Van Vaerenbergh

IPC: G06N10/00 ,  G06F9/455

CPC classification number: G06N10/00 ,  G06F9/455

Abstract: Systems and methods are configured to provide a first problem to be solved to a network of memristors. A second problem to be solved can be gradually provided to the network of memristors. Controlled noise can be applied to the network of memristors for at least a portion of time during which the second problem is “gradually” provided to the network of memristors. A solution to the second problem can be determined.

公开(公告)号：US11783907B2

公开(公告)日：2023-10-10

申请号：US17514847

申请日：2021-10-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Giacomo Pedretti ,  John Paul Strachan ,  Catherine Graves

IPC: G11C27/00 ,  G11C15/04

CPC classification number: G11C27/005 ,  G11C15/046

Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.

公开(公告)号：US20230289090A1

公开(公告)日：2023-09-14

申请号：US17691642

申请日：2022-03-10

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Giacomo Pedretti ,  John Paul Strachan ,  Thomas Maurits M. Van Vaerenbergh ,  Catherine E. Graves

IPC: G06F3/06 ,  G06N3/063

CPC classification number: G06F3/0655 ,  G06N3/063 ,  G06F3/0604 ,  G06F3/0673

Abstract: A system for facilitating an enhanced k-SAT solver is provided. The system can include a set of analog content addressable memory (aCAM) modules that can represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression. The system can also include a set of data lines that can provide input candidate values to the set of aCAM modules. A controller of the system can program the set of aCAM modules with respective analog values to represent the expression. The system can also include sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules. The controller can then iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.

公开(公告)号：US11735281B2

公开(公告)日：2023-08-22

申请号：US17245540

申请日：2021-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Catherine Graves ,  Can Li ,  John Paul Strachan

IPC: G11C27/00 ,  G11C15/04

CPC classification number: G11C27/005 ,  G11C15/046

Abstract: An analog content addressable memory (aCAM) that enables parallel searching of analog ranges of values and generates analog outputs that quantify matches between input data and stored data is disclosed. The input data can be compared with the stored data, and the input data can be determined to match the stored data based on a value associated with the input data being within a range associated with the stored data. The aCAM can generate an analog output that represents a number of matches and a number of mismatches between the input data and the stored data. Based on the analog output, whether the input data matches the stored data and a degree to which the input data matches the stored data can be determined.

公开(公告)号：US11650953B2

公开(公告)日：2023-05-16

申请号：US17072918

申请日：2020-10-16

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dejan S. Milojicic ,  Kirk M. Bresniker ,  Paolo Faraboschi ,  John Paul Strachan

IPC: G06F15/78 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F15/7867 ,  G06F9/30145 ,  G06F9/3897

Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.

公开(公告)号：US11615827B2

公开(公告)日：2023-03-28

申请号：US17071924

申请日：2020-10-15

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Catherine Graves ,  Can Li ,  Kivanc Ozonat ,  John Paul Strachan

IPC: G11C15/04 ,  G11C11/00 ,  G06F9/38 ,  G11C11/06 ,  G11C11/412

Abstract: Examples described herein relate to a decision tree computation system in which a hardware accelerator for a decision tree is implemented in the form of an analog Content Addressable Memory (a-CAM) array. The hardware accelerator accesses a decision tree. The decision tree comprises of multiple paths and each path of the multiple paths includes a set of nodes. Each node of the decision tree is associated with a feature variable of multiple feature variables of the decision tree. The hardware accelerator combines multiple nodes among the set of nodes with a same feature variable into a combined single node. Wildcard values are replaced for feature variables not being evaluated in each path. Each combined single node associated with each feature variable is mapped to a corresponding column in the a-CAM array and the multiple paths of the decision tree to rows of the a-CAM array.