公开(公告)号：US20100159685A1

公开(公告)日：2010-06-24

申请号：US12340113

申请日：2008-12-19

申请人： Harry Chuang ,  Kong-Beng Thei

发明人： Harry Chuang ,  Kong-Beng Thei

IPC分类号： H01L21/28

CPC分类号： H01L29/4238 ,  H01L21/823437 ,  H01L27/0207

摘要： A method of forming an integrated circuit structure includes providing a substrate including a first active region and a second active region; forming a gate electrode layer over the substrate; and etching the gate electrode layer. The remaining portions of the gate electrode layer include a first gate strip and a second gate strip substantially parallel to each other; and a sacrificial strip unparallel to, and interconnecting, the first gate strip and the second gate strip. The sacrificial strip is between the first active region and the second active region. The method further includes forming a mask layer covering portions of the first gate strip and the second gate strip, wherein the sacrificial strip and portions of the first gate strip and the second gate strip are exposed through an opening in the mask layer; and etching the sacrificial strip and the portions of the first gate strip and the second gate strip through the opening.

摘要翻译： 形成集成电路结构的方法包括提供包括第一有源区和第二有源区的衬底; 在所述衬底上形成栅电极层; 并蚀刻栅电极层。 栅极电极层的其余部分包括彼此基本平行的第一栅极条和第二栅极条; 以及不平行于并互连第一栅极条和第二栅极条的牺牲条。 牺牲条在第一有源区和第二有源区之间。 所述方法还包括形成覆盖所述第一栅极条和所述第二栅极条的部分的掩模层，其中所述牺牲条和所述第一栅极条和所述第二栅极条的部分通过所述掩模层中的开口暴露; 并且蚀刻所述牺牲条和所述第一栅极条和所述第二栅极条的所述部分通过所述开口。

公开(公告)号：US20100078695A1

公开(公告)日：2010-04-01

申请号：US12331109

申请日：2008-12-09

申请人： Oscar M. K. Law ,  Kong-Beng Thei ,  Harry Chuang

发明人： Oscar M. K. Law ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate including a first region and a second region; an insulation region in the second region of the semiconductor substrate; and an inter-layer dielectric (ILD) over the insulation region. A transistor is in the first region. The transistor includes a gate dielectric and a gate electrode over the gate dielectric. A first conductive line and a second conductive line are over the insulation region. The first conductive line and the second conductive line are substantially parallel to each other and extending in a first direction. A first metal line and a second metal line are in a bottom metal layer (M1) and extending in the first direction. The first metal line and the second metal line substantially vertically overlap the first conductive line and the second conductive line, respectively. The first metal line and the second metal line form two capacitor electrodes of a capacitor.

摘要翻译： 集成电路结构包括包括第一区域和第二区域的半导体衬底; 半导体衬底的第二区域中的绝缘区域; 和绝缘区域上的层间电介质（ILD）。 晶体管处于第一区域。 晶体管包括栅极电介质和位于栅极电介质上的栅电极。 第一导线和第二导线在绝缘区上方。 第一导线和第二导线基本上彼此平行并沿第一方向延伸。 第一金属线和第二金属线位于底部金属层（M1）中并沿第一方向延伸。 第一金属线和第二金属线分别基本上垂直地与第一导线和第二导线重叠。 第一金属线和第二金属线形成电容器的两个电容器电极。

公开(公告)号：US20100062577A1

公开(公告)日：2010-03-11

申请号：US12270466

申请日：2008-11-13

申请人： Shun-Jang Liao ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Shun-Jang Liao ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Provided is a method of fabricating a semiconductor device including a high-k metal gate structure. A substrate is provided including a dummy gate structure (e.g., a sacrificial polysilicon gate), a first and second hard mask layer overlie the dummy gate structure. In one embodiment, a strained region is formed on the substrate. After forming the strained region, the second hard mask layer may be removed. A source/drain region may be formed. An ILD layer is then formed on the substrate. A CMP process may planarize the ILD layer using the first hard mask layer as a stop layer. The CMP process may be continued to remove the first hard mask layer. The dummy gate structure is then removed and a metal gate provided.

摘要翻译： 提供一种制造包括高k金属栅极结构的半导体器件的方法。 提供了包括伪栅极结构（例如，牺牲多晶硅栅极），覆盖在虚拟栅极结构上的第一和第二硬掩模层的衬底。 在一个实施例中，在基底上形成应变区域。 形成应变区后，可以除去第二硬掩模层。 可以形成源极/漏极区域。 然后在衬底上形成ILD层。 CMP工艺可以使用第一硬掩模层作为停止层来平坦化ILD层。 CMP工艺可以继续去除第一硬掩模层。 然后去除虚拟栅极结构并提供金属栅极。

公开(公告)号：US20090298243A1

公开(公告)日：2009-12-03

申请号：US12468131

申请日：2009-05-19

申请人： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

发明人： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/78636

摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

摘要翻译： 提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。 在衬底上形成第一绝缘层。 在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。 在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。 在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。 第一电介质层形成在每个半导体岛的一部分上。 导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。 一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

公开(公告)号：US20080305599A1

公开(公告)日：2008-12-11

申请号：US12193538

申请日：2008-08-18

申请人： Harry Chuang ,  Kong-Beng Thei

发明人： Harry Chuang ,  Kong-Beng Thei

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L21/823437 ,  H01L27/0207 ,  H01L29/4966 ,  Y10S438/917

摘要： A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed.

摘要翻译： 形成半导体结构的方法包括以下步骤。 在有源区中的衬底上形成栅介电层。 栅极电极层形成在栅极介电层上。 在栅电极层上形成第一光刻胶。 蚀刻栅极电极层和电介质层，从而形成栅极结构和虚拟图案，其中虚拟图案中的至少一个具有活性区域中的至少一部分。 第一个光刻胶被去除。 形成覆盖栅极结构的第二光致抗蚀剂。 去除不受第二光致抗蚀剂保护的虚拟图案。 然后移除第二个光刻胶。

公开(公告)号：US20080042123A1

公开(公告)日：2008-02-21

申请号：US11699611

申请日：2007-01-30

申请人： Kong-Beng Thei ,  Harry Chuang ,  Yuan-Chen Sun

发明人： Kong-Beng Thei ,  Harry Chuang ,  Yuan-Chen Sun

IPC分类号： H01L31/00

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit includes a semiconductor substrate having a first region, at least one p-type region in the semiconductor substrate having SiGe regions formed therein, and at least one n-type region in the semiconductor substrate. All SiGe regions in the first region have a first combined area. All p-type regions in the first region have a second combined area. All n-type regions in the first region have a third combined area. The ratio of the first combined area to a total area of the second combined area and the third combined area is less than about 30 percent.

摘要翻译： 集成电路包括具有第一区域的半导体衬底，在其中形成有SiGe区域的半导体衬底中的至少一个p型区域和半导体衬底中的至少一个n型区域。 第一个地区的所有SiGe地区都有第一个合并区域。 第一区域中的所有p型区域具有第二组合区域。 第一个区域的所有n型区域都有第三个合并区域。 第一组合面积与第二组合面积和第三组合面积的总面积的比例小于约30％。

公开(公告)号：US20060163734A1

公开(公告)日：2006-07-27

申请号：US11041585

申请日：2005-01-24

申请人： Kong-Beng Thei ,  Chung-Long Cheng ,  Chung-Shi Liu ,  Harry Chuang

发明人： Kong-Beng Thei ,  Chung-Long Cheng ,  Chung-Shi Liu ,  Harry Chuang

IPC分类号： H01L23/48

CPC分类号： H01L23/5258 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a fuse structure and a method for manufacturing the fuse structure. In one example, the method includes providing a multilayer interconnect structure (MLI) over a semiconductor substrate. The MLI includes multiple fuse connection and bonding connection features. A passivation layer is formed over the MLI and patterned to form openings, with each opening being aligned with one of the fuse connection or bonding connection features. A conductive layer is formed on the passivation layer and in the openings. The conductive layer is patterned to form bonding features and fuse structures. Each bonding feature is in contact with one of the bonding connection features, and each fuse structure is in contact with two of the fuse connection features. A cap dielectric layer is formed over the fuse structures and patterned to expose at least one of the bonding features while leaving the fuse structures covered.

摘要翻译： 提供了一种熔丝结构和用于制造熔丝结构的方法。 在一个示例中，该方法包括在半导体衬底上提供多层互连结构（MLI）。 MLI包括多个保险丝连接和接合连接功能。 钝化层形成在MLI上方并被图案化以形成开口，其中每个开口与保险丝连接或接合连接特征中的一个对准。 在钝化层和开口中形成导电层。 将导电层图案化以形成结合特征和熔丝结构。 每个接合特征与接合连接特征之一接触，并且每个熔断器结构与两个熔断器连接特征接触。 在熔丝结构之上形成盖电介质层，并将其图案化以暴露粘合特征中的至少一个，同时保留熔丝结构。

公开(公告)号：US09117840B2

公开(公告)日：2015-08-25

申请号：US13399394

申请日：2012-02-17

申请人： Chen-Pin Hsu ,  Kong-Beng Thei ,  Harry Chuang

发明人： Chen-Pin Hsu ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

摘要翻译： 本公开提供了一种制造半导体器件的方法，该方法包括在硅衬底上形成栅极叠层，在栅极叠层的侧壁上形成虚设间隔物，各向同性地蚀刻硅衬底以在栅叠层的任一侧上形成凹陷区，形成 在所述凹部区域中的半导体材料，所述半导体材料与所述硅衬底不同，去除所述虚设衬垫，在所述栅极堆叠和所述半导体材料上形成具有氧化物 - 氮化物 - 氧化物构造的间隔层，并蚀刻所述间隔层以形成 栅极叠层的侧壁上的栅极间隔物。

公开(公告)号：US08487382B2

公开(公告)日：2013-07-16

申请号：US13292665

申请日：2011-11-09

申请人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/70

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/66545

摘要： The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.

摘要翻译： 本公开提供了制造半导体器件的金属栅叠层的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成导电材料层; 在n型场效应晶体管（nFET）区域中形成伪栅极，在使用多晶硅的pFET区域中形成第二伪栅极; 在所述半导体衬底上形成层间电介质（ILD）材料; 对半导体衬底施加第一化学机械抛光（CMP）工艺; 从第一伪栅极去除多晶硅，产生第一栅极沟槽; 在第一栅极沟槽上形成n型金属; 对所述半导体衬底施加第二CMP工艺; 从第二伪栅极去除多晶硅，产生第二栅极沟槽; 在所述第二栅极沟槽中形成p型金属; 以及对所述半导体衬底施加第三CMP处理。

公开(公告)号：US08334572B2

公开(公告)日：2012-12-18

申请号：US13216034

申请日：2011-08-23

申请人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L23/62

CPC分类号： H01L23/5256 ,  H01L21/823878 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity.

摘要翻译： 提供了一种半导体器件，其包括半导体衬底，形成在衬底中用于隔离衬底的有源区的隔离结构，隔离结构由第一材料形成，有源器件形成在衬底的有源区中， 具有高k电介质和金属栅极的有源器件和形成在隔离结构中的无源器件，无源器件由不同于第一材料并具有预定电阻率的第二材料形成。