公开(公告)号：US08551838B2

公开(公告)日：2013-10-08

申请号：US13064559

申请日：2011-03-31

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

公开(公告)号：US08293601B2

公开(公告)日：2012-10-23

申请号：US13010466

申请日：2011-01-20

申请人： Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7923 ,  H01L29/7926

摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.

摘要翻译： 非易失性半导体存储装置具有多个具有串联连接的多个电可重写存储单元的存储器串。 每个存储器串包括：在垂直于衬底的方向上延伸的存储器柱状半导体; 与记录柱状半导体接触的隧道绝缘层; 与隧道绝缘层接触并积累电荷的电荷累积层; 与电荷累积层接触的块绝缘层; 以及与块绝缘层接触的多个存储器导电层。 电荷累积层的下部被隧道绝缘层和块绝缘层覆盖。

公开(公告)号：US08148789B2

公开(公告)日：2012-04-03

申请号：US12260589

申请日：2008-10-29

申请人： Masaru Kito ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Masaru Kito ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L21/02

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11556

摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.

摘要翻译： 非易失性半导体存储装置具有多个具有串联连接的多个电可重写存储单元的存储器串。 每个存储器串包括：在垂直于衬底的方向上延伸的第一柱状半导体层; 电荷累积层，经由第一气隙形成在第一柱状半导体层上，并积累电荷; 与电荷累积层接触的块绝缘层; 以及与块绝缘层接触的多个第一导电层。

公开(公告)号：US20110287597A1

公开(公告)日：2011-11-24

申请号：US13064559

申请日：2011-03-31

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L29/788

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

公开(公告)号：US07768063B2

公开(公告)日：2010-08-03

申请号：US12248577

申请日：2008-10-09

申请人： Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/94

CPC分类号： H01L29/0847 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a semiconductor substrate; a first conductive layer provided on a surface of the substrate and serving as one of a source and a drain; a first insulating film provided on the first conductive layer; a gate electrode film provided on the first insulating film; a second insulating film provided on the gate electrode film; a gate opening provided so as to penetrate the second insulating film, the gate electrode film and the first insulating film to expose a part of the first conductive layer; a recess provided in the surface of the first conductive layer just below the gate opening; a gate insulator provided on the side surface of the gate opening and having a projecting shape at a portion between the first insulating film and the recess; a second conductive layer buried in the recess and in a bottom of the gate opening so as to be in contact with the gate insulator.

摘要翻译： 一种半导体器件，包括：半导体衬底; 设置在所述基板的表面上并用作源极和漏极之一的第一导电层; 设置在所述第一导电层上的第一绝缘膜; 设置在所述第一绝缘膜上的栅电极膜; 设置在栅电极膜上的第二绝缘膜; 设置为穿透第二绝缘膜的栅极开口，栅极电极膜和第一绝缘膜，以暴露第一导电层的一部分; 设置在所述第一导电层的位于所述栅极开口正下方的表面中的凹部; 栅极绝缘体，其设置在所述栅极开口的侧表面上，并且在所述第一绝缘膜和所述凹部之间的部分处具有突出形状; 第二导电层，其埋在所述凹部中并位于所述栅极开口的底部，以与所述栅极绝缘体接触。

公开(公告)号：US08294191B2

公开(公告)日：2012-10-23

申请号：US12943349

申请日：2010-11-10

申请人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

发明人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar. The first and second connection portion memory layers are provided between the connection portion conductive layers and the semiconductor connection portion.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构，第一和第二半导体柱，半导体连接部分，第一和第二连接部分导电层，第一和第二柱部存储器 层，第一和第二连接部分存储层。 第一和第二堆叠结构包括在第一方向上交替堆叠的电极膜和电极间绝缘膜。 第二堆叠结构与第一堆叠结构相邻。 第一和第二半导体柱分别刺穿第一和第二堆叠结构。 半导体连接部分连接第一和第二半导体柱。 第一和第二柱部存储层设置在电极膜和半导体柱之间。 第一和第二连接部分存储层设置在连接部分导电层和半导体连接部分之间。

公开(公告)号：US20120043599A1

公开(公告)日：2012-02-23

申请号：US12943349

申请日：2010-11-10

申请人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

发明人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar. The first and second connection portion memory layers are provided between the connection portion conductive layers and the semiconductor connection portion.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构，第一和第二半导体柱，半导体连接部分，第一和第二连接部分导电层，第一和第二柱部存储器 层，第一和第二连接部分存储层。 第一和第二堆叠结构包括在第一方向上交替堆叠的电极膜和电极间绝缘膜。 第二堆叠结构与第一堆叠结构相邻。 第一和第二半导体柱分别刺穿第一和第二堆叠结构。 半导体连接部分连接第一和第二半导体柱。 第一和第二柱部存储层设置在电极膜和半导体柱之间。 第一和第二连接部分存储层设置在连接部分导电层和半导体连接部分之间。

公开(公告)号：US08669608B2

公开(公告)日：2014-03-11

申请号：US13419984

申请日：2012-03-14

申请人： Mitsuru Sato ,  Megumi Ishiduki ,  Masaru Kidoh ,  Atsushi Konno ,  Yoshihiro Akutsu ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata

发明人： Mitsuru Sato ,  Megumi Ishiduki ,  Masaru Kidoh ,  Atsushi Konno ,  Yoshihiro Akutsu ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L21/265 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/66833

摘要： According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.

摘要翻译： 根据一个实施例，一种用于制造非易失性半导体存储装置的方法包括： 形成第一和第二堆叠体; 形成穿过所述第一层叠体的通孔，与所述第一部分连通并穿过选择栅极的第二部分，以及与所述第二部分连通并穿透第二绝缘层的第三部分; 形成记忆膜，栅极绝缘膜和通道体; 在通道体内形成第三绝缘层; 在第三部分内部的边界部分上方形成第一嵌入部分; 通过去除第三部分中的第一嵌入部分和第三绝缘层的一部分的一部分来暴露通道体; 以及在所述第三部分内部嵌入包含比所述第一嵌入部分上方的所述第一嵌入部分杂质浓度高的硅的第二嵌入部分。

公开(公告)号：US08378406B2

公开(公告)日：2013-02-19

申请号：US12717499

申请日：2010-03-04

申请人： Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Masaru Kito ,  Hideaki Aochi

发明人： Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Masaru Kito ,  Hideaki Aochi

IPC分类号： H01L29/76

CPC分类号： H01L27/11578 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/792

摘要： A nonvolatile semiconductor memory device includes: a substrate; a memory multilayer body with a plurality of insulating films and electrode films alternately stacked therein, the memory multilayer body being provided on a memory array region of the substrate; a semiconductor pillar buried in the memory multilayer body and extending in stacking direction of the insulating films and the electrode films; a charge storage film provided between one of the electrode films and the semiconductor pillar; a dummy multilayer body with a plurality of the insulating films and the electrode films alternately stacked therein and a dummy hole formed therein, the dummy multilayer body being provided on a peripheral circuit region of the substrate; an insulating member buried in the dummy hole; and a contact buried in the insulating member and extending in the stacking direction.

摘要翻译： 非易失性半导体存储器件包括：衬底; 具有交替堆叠的多个绝缘膜和电极膜的存储器多层体，所述存储器多层体设置在所述衬底的存储器阵列区域上; 埋入存储器多层体中并在绝缘膜和电极膜的堆叠方向上延伸的半导体柱; 设置在所述电极膜和所述半导体柱之间的电荷存储膜; 具有多个绝缘膜和电极膜交替堆叠的虚设多层体和形成在其中的虚拟孔，所述虚设多层体设置在所述基板的外围电路区域上; 埋在虚拟孔中的绝缘构件; 以及埋入绝缘构件中并沿堆叠方向延伸的触点。

公开(公告)号：US08334551B2

公开(公告)日：2012-12-18

申请号：US13120987

申请日：2009-08-25

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

IPC分类号： H01L29/792 ,  G11C11/34

CPC分类号： H01L27/1157 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/7926

摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n

摘要翻译： 每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。 对于每个存储块，存储器串按第二方向布置有m列。 布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。 满足式（1）所示的关系：（式1）m> = n