公开(公告)号：US08592320B2

公开(公告)日：2013-11-26

申请号：US13210172

申请日：2011-08-15

申请人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/302

CPC分类号： H01L29/7854 ,  H01L29/7853

摘要： A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.

摘要翻译： 提供了一种制造鳍状半导体结构的方法，包括：提供半导体衬底和形成在其上的介电层的半导体衬底; 在所述半导体岛和所述电介质层上形成掩模层; 在所述掩模层中形成开口，使所述半导体岛的上表面和与所述半导体岛相邻的所述电介质层的部分露出; 进行蚀刻处理，同时蚀刻掩模层的一部分，以及由开口暴露的半导体岛和电介质层的部分; 并且去除掩模层和电介质层，在半导体衬底上留下具有弯曲顶表面和各种厚度的蚀刻半导体岛。

公开(公告)号：US08546234B2

公开(公告)日：2013-10-01

申请号：US13154427

申请日：2011-06-06

申请人： Wen-Chieh Wang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Wen-Chieh Wang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/20

CPC分类号： H01L29/66621 ,  H01L21/26506 ,  H01L21/26513 ,  H01L27/10876

摘要： A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.

摘要翻译： 提供半导体工艺。 在衬底上形成掩模层，并且具有暴露衬底的一部分的第一开口。 使用掩模层作为掩模，在基板上进行干蚀刻处理，以在其中形成第二开口。 第二开口具有底部和从底部向上并向外延伸的侧壁，其中底部由第一开口暴露，并且侧壁被掩模层覆盖。 使用掩模层作为掩模，在底部进行垂直离子注入工艺。 进行转换处理，以在第二开口的侧壁和底部形成转换层，其中侧壁上的转换层的厚度大于底部上的转换层的厚度。

公开(公告)号：US08545289B2

公开(公告)日：2013-10-01

申请号：US13086367

申请日：2011-04-13

申请人： Chien-Mao Liao ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chien-Mao Liao ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B24B49/00

CPC分类号： H01L21/67259 ,  B24B37/005 ,  B24B37/30 ,  B24B49/08 ,  B24B49/10 ,  B24B49/12 ,  H01L21/68735

摘要： A distance monitoring device is provided. The device is suitable for a chemical mechanical polishing (CMP) apparatus. A polishing head of the CMP apparatus includes a frame and a membrane. The membrane is mounted on the frame, and a plurality of air bags is formed by the membrane and the frame in the polishing head. The distance monitoring device includes a plurality of distance detectors disposed on the frame corresponding to the air bags respectively to set a location of each of the distance detectors on the frame as a reference point, wherein each of the distance detectors is configured to measure a distance between each of the reference points and the membrane.

摘要翻译： 提供了一种距离监测装置。 该设备适用于化学机械抛光（CMP）设备。 CMP设备的抛光头包括框架和膜。 膜安装在框架上，并且多个气囊由抛光头中的膜和框架形成。 距离监视装置包括多个距离检测器，其分别布置在与气囊对应的框架上，以将每个距离检测器的位置设置在框架上作为参考点，其中每个距离检测器被配置成测量距离 在每个参考点和膜之间。

公开(公告)号：US20130102123A1

公开(公告)日：2013-04-25

申请号：US13276960

申请日：2011-10-19

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/02

CPC分类号： H01L27/10867

摘要： A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess.

摘要翻译： 一种掩埋带的制造方法包括：在半导体衬底中形成沟槽电容器结构，其中沟槽电容器结构具有掺杂多晶硅层和由掺杂多晶硅层覆盖的隔离环，以及掺杂多晶硅层的顶表面 低于半导体衬底的顶表面，从而形成第一凹槽; 在半导体衬底上依次形成第一抗蚀剂层，第二抗蚀剂层和第三抗蚀剂层; 顺序地图案化第三抗蚀剂层，第二抗蚀剂层和第一抗蚀剂层，在半导体衬底上形成图案化的三层抗蚀剂层; 部分地去除由图案化的三层抗蚀剂层暴露的部分掺杂多晶硅层以形成第二凹槽; 去除图案化的三层抗蚀剂层; 以及在所述第二凹部中形成绝缘层和所述第一凹部的一部分。

公开(公告)号：US20130078774A1

公开(公告)日：2013-03-28

申请号：US13240931

申请日：2011-09-22

申请人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/223 ,  H01L21/268 ,  H01L21/823814

摘要： The invention provides a method for forming a semiconductor device, including providing a substrate, forming a gate dielectric layer, forming a gate electrode on the gate dielectric layer, forming a spacer on sidewalls of the gate dielectric layer and the gate electrode, and using a rapid thermal process (RTP) apparatus comprising a plurality of lamps and a bias applying system to dope the substrate to form a source/drain region, wherein in the RTP apparatus, gaseous dopant species are illuminated by the lamps to be excited for transference gaseous dopant species to dopant ions and the dopant ions are moved by a bias from the bias applying system to be doped into the substrate.

摘要翻译： 本发明提供一种用于形成半导体器件的方法，包括提供衬底，形成栅极电介质层，在栅极电介质层上形成栅电极，在栅极电介质层和栅电极的侧壁上形成间隔物，并使用 包括多个灯的快速热处理（RTP）装置和用于掺杂衬底以形成源极/漏极区域的偏置施加系统，其中在RTP装置中，气体掺杂物质被待激发的灯照射以用于转移气体掺杂剂 物质与掺杂剂离子和掺杂剂离子通过来自偏置施加系统的偏压移动以掺杂到衬底中。

公开(公告)号：US20130071992A1

公开(公告)日：2013-03-21

申请号：US13237975

申请日：2011-09-21

申请人： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/762

CPC分类号： H01L21/762 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02664

摘要： A semiconductor process is provided. An insulating layer is formed on a semiconductor substrate. A portion of the insulating layer is removed, so as to form a plurality of isolation structures and a mesh opening disposed between the isolation structures and exposing the semiconductor substrate. By performing a selective growth process, a semiconductor layer is formed from a surface of the semiconductor substrate exposed by the mesh opening, so that the isolation structures are disposed in the semiconductor layer.

摘要翻译： 提供半导体工艺。 绝缘层形成在半导体衬底上。 去除绝缘层的一部分，以便形成多个隔离结构和布置在隔离结构之间并露出半导体衬底的网孔。 通过进行选择性生长处理，从由网眼露出的半导体衬底的表面形成半导体层，使得隔离结构设置在半导体层中。

公开(公告)号：US20130071790A1

公开(公告)日：2013-03-21

申请号：US13233039

申请日：2011-09-15

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： G03F7/20

CPC分类号： G03F7/094 ,  G03F7/095 ,  G03F7/32 ,  G03F7/38 ,  H01L21/0275 ,  H01L21/0277 ,  H01L21/32139

摘要： A method of forming an etch mask includes: providing a substrate having thereon a material layer to be etched; forming a hard mask layer consisting of a radiation-sensitive, single-layer resist material on the material layer; exposing the hard mask layer to actinic energy to change solvent solubility of exposed regions of the hard mask layer; and subjecting the hard mask layer to water treatment to remove the exposed regions of the hard mask layer, thereby forming a masking pattern consisting of unexposed regions of the hard mask layer.

摘要翻译： 形成蚀刻掩模的方法包括：提供其上具有要蚀刻的材料层的基板; 在材料层上形成由辐射敏感的单层抗蚀剂材料组成的硬掩模层; 将硬掩模层暴露于光化能以改变硬掩模层的暴露区域的溶剂溶解度; 并对硬掩模层进行水处理以除去硬掩模层的暴露区域，从而形成由硬掩模层的未曝光区域构成的掩模图案。

公开(公告)号：US20130069235A1

公开(公告)日：2013-03-21

申请号：US13235491

申请日：2011-09-18

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L23/485

CPC分类号： H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05085 ,  H01L2224/05095 ,  H01L2224/05624

摘要： A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; anda plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.

摘要翻译： 焊盘结构包括其上具有包括至少最上面的IMD层的多个金属间电介质（IMD）层的半导体衬底; 可焊接金属焊盘层，其设置在焊盘形成区域内的最上层IMD层的表面上; 覆盖可焊接金属焊盘层的周边和最上面的IMD层的表面的钝化层; 以及设置在焊盘形成区域的环形区域内的最上层IMD层中的多个通孔，其中通孔塞不形成在焊盘形成区域的中心区域中。

公开(公告)号：US20130017684A1

公开(公告)日：2013-01-17

申请号：US13179581

申请日：2011-07-11

申请人： Wen-Chieh Wang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Wen-Chieh Wang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/306

CPC分类号： H01L21/3065 ,  H01L21/3085

摘要： A process of forming a slit in a substrate is provided. A mask layer is formed on a substrate, wherein the mask layer does not include carbon. An etching process is performed to be substrate by using the mask layer as a mask, so as to form a slit in the substrate. The etching gas includes Cl2, CF4 and CHF3, a molar ratio of CF4 to CHF3 is about 0.5-0.8, and a molar ratio of F to Cl is about 0.4-0.8, for example. Further, the step of performing the etching process simultaneously removes the mask layer.

摘要翻译： 提供了在基板中形成狭缝的工艺。 在基板上形成掩模层，其中掩模层不包括碳。 通过使用掩模层作为掩模，进行蚀刻处理，以便在衬底中形成狭缝。 蚀刻气体包括Cl 2，CF 4和CHF 3，CF 4与CHF 3的摩尔比为约0.5-0.8，F与Cl的摩尔比例如约为0.4-0.8。 此外，进行蚀刻处理的步骤同时去除掩模层。

公开(公告)号：US20120309192A1

公开(公告)日：2012-12-06

申请号：US13154427

申请日：2011-06-06

申请人： Wen-Chieh Wang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Wen-Chieh Wang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/768

CPC分类号： H01L29/66621 ,  H01L21/26506 ,  H01L21/26513 ,  H01L27/10876

摘要： A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.

摘要翻译： 提供半导体工艺。 在衬底上形成掩模层，并具有暴露衬底的一部分的第一开口。 使用掩模层作为掩模，在基板上进行干蚀刻处理，以在其中形成第二开口。 第二开口具有底部和从底部向上并向外延伸的侧壁，其中底部由第一开口暴露，并且侧壁被掩模层覆盖。 使用掩模层作为掩模，在底部进行垂直离子注入工艺。 进行转换处理，以在第二开口的侧壁和底部形成转换层，其中侧壁上的转换层的厚度大于底部上的转换层的厚度。