公开(公告)号：US20220206853A1

公开(公告)日：2022-06-30

申请号：US17520583

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Abhishek R Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06F9/48 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US11263141B2

公开(公告)日：2022-03-01

申请号：US17026264

申请日：2020-09-20

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126 ,  G06F12/0893

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

公开(公告)号：US11169850B2

公开(公告)日：2021-11-09

申请号：US16726341

申请日：2019-12-24

Applicant: Intel Corporation

Inventor： Abhishek R Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06F9/48 ,  G06T1/20 ,  G06T15/00 ,  G06T1/60

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US11074891B2

公开(公告)日：2021-07-27

申请号：US16588507

申请日：2019-09-30

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Altug Koker ,  Kiran C. Veernapu ,  Erik G. Liskay

IPC: G09G5/39 ,  G06F3/14 ,  G06T1/20 ,  G09G5/393

Abstract: A mechanism is described for facilitating consolidated compression/de-compression of graphics data streams of varying types at computing devices. A method of embodiments, as described herein, includes generating a common sector cache relating to a graphics processor. The method may further include performing a consolidated compression of multiple types of graphics data streams associated with the graphics processor using the common sector cache.

公开(公告)号：US11055248B2

公开(公告)日：2021-07-06

申请号：US16599261

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kiran C. Veernapu ,  Balaji Vembu ,  Vasanth Ranganathan ,  Prasoonkumar Surti

IPC: G06F13/40 ,  G06F9/54 ,  G06F13/42 ,  G06T1/60 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0831

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to monitor a thread switching overhead parameter for an application executing in a processing system and in response to a determination that the thread switching overhead parameter exceeds a threshold, to activate a thread management algorithm to reduce thread switching in the processing system. Other embodiments are also disclosed and claimed.

公开(公告)号：US11010163B2

公开(公告)日：2021-05-18

申请号：US16526147

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kamal Sinha ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  David Puffer ,  Supratim Pal ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

IPC: G06F9/30 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F9/46 ,  G09G5/36 ,  G06F9/38

Abstract: Disclosed herein is an apparatus which comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units.

公开(公告)号：US10852806B2

公开(公告)日：2020-12-01

申请号：US16661803

申请日：2019-10-23

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Kiran C. Veernapu ,  Eric J. Asperheim ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06F15/00 ,  G06F1/3234 ,  G06F9/46 ,  G06F1/329

Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.

公开(公告)号：US10817296B2

公开(公告)日：2020-10-27

申请号：US15493467

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Ramkumar Ravikumar ,  Kiran C. Veernapu ,  Prasoonkumar Surti ,  Vasanth Ranganathan

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F13/36 ,  G06F13/40 ,  G06F15/76

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to assemble a general register file (GRF) message and hold the GRF message in storage in a data port until all data for the GRF message is received. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200272215A1

公开(公告)日：2020-08-27

申请号：US16805480

申请日：2020-02-28

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G06F1/3209 ,  H04W52/02 ,  G06F1/324 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F3/01 ,  G06F11/07 ,  G06F11/30

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200183849A1

公开(公告)日：2020-06-11

申请号：US16702073

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06T1/60 ,  G06F12/0868 ,  G06F12/0846 ,  G06F12/0806 ,  G06F12/0855 ,  G06F12/0802 ,  G06F12/126

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.