公开(公告)号：US20210242277A1

公开(公告)日：2021-08-05

申请号：US16780684

申请日：2020-02-03

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja De Silva ,  Dominik Metzler

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: Techniques for integrating an embedded MRAM device with a BEOL interconnect structure are provided. In one aspect, a method of forming an embedded MRAM device includes: depositing a cap layer onto a substrate; forming a metal line and metal pad on the cap layer; patterning the metal line to form first top vias, and the metal pad to form a second top via; depositing a dielectric material onto the substrate surrounding the first/second top vias; recessing the second top via to form a bottom contact via self-aligned to the metal pad which serves as a bottom contact; forming an MRAM cell over the bottom contact via; and forming first/second top contacts in contact with the first top vias/the MRAM cell. An embedded MRAM device is also provided.

公开(公告)号：US20210233843A1

公开(公告)日：2021-07-29

申请号：US16774922

申请日：2020-01-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chih-Chao Yang ,  Baozhen Li ,  Tianji Zhou ,  Ashim Dutta ,  Saumya Sharma

IPC: H01L23/525 ,  H01L23/522 ,  H01L21/768

Abstract: An anti-fuse device having enhanced programming efficiency is provided. The anti-fuse device includes via contact structures that have different critical dimensions located between a first electrode and a second electrode. Notably, a first via contact structure having a first critical dimension is provided between a pair of second via contact structures having a second critical dimension that is greater than the first critical dimension. When a voltage is applied to the device, dielectric breakdown will occur first through the first via contact structure having the first critical dimension.

公开(公告)号：US11043628B2

公开(公告)日：2021-06-22

申请号：US16595572

申请日：2019-10-08

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja De Silva

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Provided are embodiments for a semiconductor device that includes a bottom contact; a multi-layer bottom electrode formed over the bottom contact; a magnetic tunnel junction stack formed over the multi-layer bottom electrode; and a top electrode formed over the magnetic tunnel junction stack. Also provided are embodiments for forming the semiconductor device described herein.

公开(公告)号：US10892404B1

公开(公告)日：2021-01-12

申请号：US16506459

申请日：2019-07-09

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saba Zare ,  Michael Rizzolo ,  Theodorus E. Standaert ,  Daniel Charles Edelstein

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/10

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.

公开(公告)号：US10833258B1

公开(公告)日：2020-11-10

申请号：US16402126

申请日：2019-05-02

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Daniel C. Edelstein ,  Karthik Yogendra ,  John C. Arnold

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01F41/34 ,  H01L43/10 ,  H01F10/32 ,  G11C11/16

Abstract: MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.

公开(公告)号：US10833257B1

公开(公告)日：2020-11-10

申请号：US16401960

申请日：2019-05-02

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  John C. Arnold ,  Chih-Chao Yang ,  Theodorus E. Standaert

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/02 ,  H01L27/12 ,  H01L27/22

Abstract: Techniques are provided for fabricating semiconductor integrated circuit devices with embedded magnetic random-access memory (MRAM) devices. For example, a MRAM device and a multi-level bottom electrode via contact are formed within a back-end-of line layer. The MRAM device includes a memory device pillar having a bottom electrode, a magnetic tunnel junction structure, and an upper electrode. The multi-level bottom electrode via contact is disposed below and in contact with the bottom electrode. The multi-level bottom electrode via contact includes a first via contact disposed in a first insulation layer, and a second via contact disposed in a second insulation layer. The first and second insulation layers allow for sacrificial etching of the first and second insulation layers during formation of the MRAM device while retaining a sufficient thickness of remaining insulation material to serve as a capping layer to protect metallic wiring that is disposed in an underlying metallization layer.

公开(公告)号：US20200350495A1

公开(公告)日：2020-11-05

申请号：US16402126

申请日：2019-05-02

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Daniel C. Edelstein ,  Karthik Yogendra ,  John C. Arnold

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  G11C11/16 ,  H01L43/10 ,  H01F10/32 ,  H01F41/34

Abstract: MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.

公开(公告)号：US20200350494A1

公开(公告)日：2020-11-05

申请号：US16401960

申请日：2019-05-02

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  John C. Arnold ,  Chih-Chao Yang ,  Theodorus E. Standaert

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16

Abstract: Techniques are provided for fabricating semiconductor integrated circuit devices with embedded magnetic random-access memory (MRAM) devices. For example, a MRAM device and a multi-level bottom electrode via contact are formed within a back-end-of line layer. The MRAM device includes a memory device pillar having a bottom electrode, a magnetic tunnel junction structure, and an upper electrode. The multi-level bottom electrode via contact is disposed below and in contact with the bottom electrode. The multi-level bottom electrode via contact includes a first via contact disposed in a first insulation layer, and a second via contact disposed in a second insulation layer. The first and second insulation layers allow for sacrificial etching of the first and second insulation layers during formation of the MRAM device while retaining a sufficient thickness of remaining insulation material to serve as a capping layer to protect metallic wiring that is disposed in an underlying metallization layer.

公开(公告)号：US20200161540A1

公开(公告)日：2020-05-21

申请号：US16194443

申请日：2018-11-19

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja de Silva ,  Jennifer Church ,  Luciana Meli Thompson

IPC: H01L43/12 ,  H01L21/02 ,  H01L43/02 ,  H01L27/22

Abstract: A method for selectively encapsulating embedded memory pillars in a semiconductor device includes coating a passivation layer on a first dielectric surface on a first outer dielectric layer present in the semiconductor device. The passivation layer adheres to the dielectric surface selective to metal. The method includes depositing an encapsulation layer on side and top surfaces of the embedded memory pillars. The passivation layer prevents deposition of the encapsulation layer on the first dielectric surface of the first outer layer dielectric. The method includes removing the first outer dielectric layer from horizontal subraces around the embedded memory pillar and the encapsulation layer from the top surface of the embedded memory pillars.

公开(公告)号：US20200058501A1

公开(公告)日：2020-02-20

申请号：US16104371

申请日：2018-08-17

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Ekmini Anuja De Silva ,  Luciana Meli Thompson

IPC: H01L21/033

Abstract: A method of manufacturing a semiconductor device includes forming a hard mask layer over a substrate and activating a surface of the hard mask layer to form a surface active layer over the hard mask layer. A resist layer is formed over the hard mask layer and a metal-containing layer is selectively formed over the surface active layer in at least one trench defined between portions of the resist layer. The resist layer is removed to define a pattern between portions of the selectively formed metal-containing layer and the hard mask layer is etched in accordance with the pattern. The etched pattern is transferred to at least a portion of the substrate and at least a portion of the hard mask layer, surface active layer, and metal-containing layer are removed.