公开(公告)号：US07587552B2

公开(公告)日：2009-09-08

申请号：US11581569

申请日：2006-10-17

申请人： Junji Ogawa

发明人： Junji Ogawa

IPC分类号： G06F12/16 ,  G06F11/30

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0683 ,  G06F11/3409 ,  G06F11/3461

摘要： A computer system includes a host computer; a first storage system that processes an I/O request issued by the host computer; and a second storage system that receives host I/O information and performance information from the first storage system and reproduces, based on the host I/O information and performance information, the internal processing conditions of the first storage system at the time the I/O request was processed, thereby simulating the I/O performance of the first storage system.

摘要翻译： 计算机系统包括主计算机; 处理由主机发出的I / O请求的第一存储系统; 以及第二存储系统，其从所述第一存储系统接收主机I / O信息和性能信息，并且基于所述主机I / O信息和性能信息，再现所述第一存储系统的内部处理条件， O请求进行处理，从而模拟第一个存储系统的I / O性能。

公开(公告)号：US07505532B2

公开(公告)日：2009-03-17

申请号：US11604807

申请日：2006-11-28

申请人： Miyoshi Saito ,  Junji Ogawa

发明人： Miyoshi Saito ,  Junji Ogawa

IPC分类号： H04L25/06 ,  H03F3/45

CPC分类号： G11C7/1063 ,  G11C7/04 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/229 ,  H04L25/03878

摘要： A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when the signal transmission line is switched between the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched. This makes continuous readout possible and achieves an increase in the overall speed of the signal transmission system.

摘要翻译： 信号传输系统被构造为通过消除由前面的数据引入的符号间干扰成分，通过信号传输线路传输数据，而不需要为每一位预充电信号传输线。 信号传输线具有以分支结构或层次结构组织的多个可切换信号传输线，从多个信号传输线中的每一个连接至少一个读取数据的目标单元，以及读出电路，包括： 用于消除符号间干扰分量的电路连接到信号传输线，其中，符号间干扰成分消除电路减少了在多个信号传输线之间切换信号传输线时引入的噪声，从而提供平滑的符号间干扰成分消除操作 当信号传输线路被切换时。 这使连续读出成为可能，并实现了信号传输系统的整体速度的提高。

公开(公告)号：US07421547B2

公开(公告)日：2008-09-02

申请号：US11246255

申请日：2005-10-11

申请人： Yuko Matsui ,  Junji Ogawa

发明人： Yuko Matsui ,  Junji Ogawa

IPC分类号： G06F12/00 ,  G11C29/00

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/067 ,  G06F3/0689 ,  G11B20/12 ,  G11B20/1217 ,  G11B2020/1297 ,  G11B2220/2516

摘要： Each storage unit is provided with a table for storing a corresponding unit ID and count value. The controller receives a formatting instruction specifying a first unit ID, and updates the count value on a table corresponding to the first unit ID. The controller receives a write command specifying a second unit ID, acquires a count value corresponding to the second unit ID from the table, and attaches the count value to the data, and writes the data to the storage unit. When a read command specifying the second unit ID is received, the controller reads the data from the storage unit, acquires the count value corresponding to the second unit ID from the table, compares this count value and the count value attached to the read data, sends the read data to the transmission source of the command if these values match, and does not send the data to the transmission source of the command if these values do not match.

摘要翻译： 每个存储单元设置有用于存储对应的单元ID和计数值的表。 控制器接收指定第一单元ID的格式化指令，并更新与第一单元ID相对应的表上的计数值。 控制器接收指定第二单元ID的写命令，从表中获取与第二单元ID相对应的计数值，并将计数值附加到数据，并将数据写入存储单元。 当接收到指定第二单元ID的读取命令时，控制器从存储单元读取数据，从表中获取与第二单元ID相对应的计数值，比较该计数值和附加到读取数据的计数值， 如果这些值匹配，则将读取的数据发送到命令的发送源，并且如果这些值不匹配，则不将数据发送到命令的发送源。

公开(公告)号：US20080092143A1

公开(公告)日：2008-04-17

申请号：US11598664

申请日：2006-11-14

申请人： Hideyuki Koseki ,  Junji Ogawa

发明人： Hideyuki Koseki ,  Junji Ogawa

IPC分类号： G06F9/46

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0689 ,  G06F11/3433 ,  G06F2201/81 ,  G06F2206/1012

摘要： This storage apparatus having a plurality of physical devices for balancing and retaining data sent from a host computer and parity of the data for each prescribed unit includes a load ratio calculation unit for calculating a load ratio of the plurality of physical devices, a load ratio determination unit for determining whether the load ratio of the physical devices calculated with the load ratio calculation unit exceeds a prescribed threshold value, a command ratio determination unit for determining whether a command ratio of either a write command or a read command issued from the host computer exceeds a prescribed threshold value when the load ratio determination unit determines that the load ratio of the physical device exceeds a prescribed threshold value, and a change unit for changing the data and the parity among the plurality of physical devices when the command ratio determination unit determines that the command ratio exceeds a prescribed threshold value.

摘要翻译： 具有用于平衡和保留从主计算机发送的数据的多个物理装置的该存储装置以及用于每个规定单元的数据的奇偶校验包括负载比率计算单元，用于计算多个物理装置的负载比，负载比确定 单元，用于确定由所述负载比计算单元计算的所述物理设备的负载比是否超过规定的阈值;命令比率确定单元，用于确定从所述主计算机发出的写入命令或读取命令的命令比是否超过 当所述负载比确定单元确定所述物理设备的负载比超过规定阈值时的规定阈值;以及改变单元，用于当所述指令比率确定单元确定所述多个物理设备之间时，改变所述多个物理设备之间的数据和奇偶校验 指令比例超过规定的阈值。

公开(公告)号：US07346599B2

公开(公告)日：2008-03-18

申请号：US11007775

申请日：2004-12-07

申请人： Junji Ogawa ,  Yusuke Nonaka

发明人： Junji Ogawa ,  Yusuke Nonaka

IPC分类号： G06F7/00

CPC分类号： G06F17/30315 ,  Y10S707/99931

摘要： The fact that data stored in a storage system is not updated for a given period is proven to a third party. A method of managing data that is given an update prohibitive attribute includes a step of storing, in a management server, information on an end time of the update prohibitive attribute which is received from a storage system, a step of receiving, from the storage system, a request for permission to change the update prohibitive attribute given to the data and obtaining, from the management server, the end time of the update prohibitive attribute given to the data on which the request is made, a step of judging whether or not the end time of the update prohibitive attribute has passed, and a step of sending, when it is judged that the end time of the update prohibitive attribute given to the data on which the request is made has passed, permission to change the update prohibitive attribute given to the data on which the request is made to the storage system.

摘要翻译： 存储在存储系统中的数据在给定时间段内未被更新的事实被证明给第三方。 一种管理被赋予更新禁止属性的数据的方法包括：在管理服务器中存储从存储系统接收到的更新禁止属性的结束时间的信息的步骤，从存储系统 ，请求许可更改给予数据的更新禁止属性，并从管理服务器获得给予对其进行请求的数据的更新禁止属性的结束时间;判断是否 更新禁止属性的结束时间已经过去，并且当判断给予对其进行请求的数据的更新禁止属性的结束时间已经通过时，发送允许改变给定的更新禁止属性 到对存储系统进行请求的数据。

公开(公告)号：US20070063779A1

公开(公告)日：2007-03-22

申请号：US11386789

申请日：2006-03-23

申请人： Kouichi Kanda ,  Hirotaka Tamura ,  Hisakatsu Yamaguchi ,  Junji Ogawa

发明人： Kouichi Kanda ,  Hirotaka Tamura ,  Hisakatsu Yamaguchi ,  Junji Ogawa

IPC分类号： H03B5/08 ,  H03B5/18

CPC分类号： H03L7/099 ,  G06F1/04 ,  G06F1/10 ,  H03L7/0805 ,  H03L7/24

摘要： LC resonant voltage control oscillators are adopted as voltage control oscillators for the purpose of providing a clock generating and distributing apparatus that can generate and distribute a clock signal of high precision even in a high-frequency region of several giga hertz or higher, and of providing a distributive VCO-type clock generating and distributing apparatus in which voltage control oscillators oscillate in the same phase, and which can generate a clock signal of a desired frequency and distributes a high-frequency clock signal to each part within a chip more stably even in a high-frequency region reaching 20 GHz. Furthermore, an inductor component of a wire connecting the oscillation nodes of the oscillators is made relatively small, or the LC resonant oscillators are oscillated in synchronization by using injection locking, whereby the LC resonant voltage control oscillators stably oscillate in the same phase.

摘要翻译： 采用LC谐振电压控制振荡器作为电压控制振荡器，用于提供即使在几千赫兹或更高的高频区域也能生成和分配高精度的时钟信号的时钟发生和分配装置，并且提供 一种分布式VCO型时钟发生和分配装置，其中电压控制振荡器以相同相位振荡，并且其可以产生期望频率的时钟信号，并且即使在 达到20GHz的高频区域。 此外，连接振荡器的振荡节点的线的电感器部件相对较小，或者LC谐振振荡器通过使用注入锁定而同步地振荡，由此LC谐振电压控制振荡器以相同的相位稳定地振荡。

公开(公告)号：US06385951B1

公开(公告)日：2002-05-14

申请号：US09543574

申请日：2000-04-05

申请人： Junji Ogawa

发明人： Junji Ogawa

IPC分类号： A01D3403

CPC分类号： A01D34/412 ,  A01D34/76

摘要： A plant mowing apparatus in which a driven case is rotationally engaged by way of a braking device to a cylindrical frame having a rotary driving shaft pivoted therein and a plurality of cutter rotary shafts each having rotary blade units joined at the top end is attached to the driven case in parallel with the rotary driving shaft, rotary bodies having predetermined circumferential ratio are fixed respectively, to the rotary driving shaft and the cutter rotary driving shaft, and the rotary body for the cutter rotary shaft and the rotary body for the rotary driving shaft are connected by way of a rotation transmitting unit, such that the cutter rotary shaft revolves under auto-rotation. The cutter unit of the rotary blade having a plurality of blade edges at the circumferential side and each of the blade edges is turned to the rotational direction for cutting by the change of the attaching angle, the rotary blade unit and the cutter rotary shaft are engaged under pressure by way of a resilient member. Vertical slits are formed to the cover in a case where a side cover is used while skids may be attached in a case of not using the side cover.

摘要翻译： 一种植物割草设备，其中从动壳体通过制动装置旋转地接合到具有枢转在其中的旋转驱动轴的圆柱形框架，并且多个在顶端连接有旋转刀片单元的切割器旋转轴附接到 驱动壳体与旋转驱动轴并联，具有规定的周向比的旋转体分别固定在旋转驱动轴和切割器旋转驱动轴上，以及用于切割器旋转轴的旋转体和用于旋转驱动轴的旋转体 通过旋转传递单元连接，使得切割旋转轴在自动旋转的状态下旋转。 旋转叶片的切割单元在周向侧具有多个叶片边缘，并且每个叶片边缘通过安装角度的改变而转动到用于切割的旋转方向，旋转刀片单元和切割器旋转轴接合 在压力下通过弹性构件。 在使用侧盖的情况下，在不使用侧盖的情况下可以安装滑板的情况下，在盖上形成有垂直的狭缝。

公开(公告)号：US06205076B1

公开(公告)日：2001-03-20

申请号：US09276690

申请日：1999-03-26

申请人： Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Miyoshi Saito ,  Junji Ogawa

发明人： Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Miyoshi Saito ,  Junji Ogawa

IPC分类号： G11C700

CPC分类号： G11C7/065 ,  G11C7/06 ,  G11C11/4091

摘要： A restoring circuit 24, provided for each of the memory blocks 191 and 192, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder 26. The present row address is held in one of the registers. When amplification is started by a sense amplifier 15, transfer gates 10 and 11 connected between the bit lines BL1 and *BL1 and the sense amplifier 15 are turned off to decrease the load of the sense amplifier 15, the amplified signal is stored in a buffer memory cell circuit 18, and accessing is completed with omitting restoring to the memory cell 12. While the memory cell block 191 is not selected, the data held in the buffer memory cell circuit 18 is stored into the memory cell row addressed by the content of the selected register. The sense amplifier 15 has PMOS and NMOS sense amplifiers. The PMOS sense amplifier, having a pair of cross-coupled PMOS transistors and a pair of transfer gates, the potential of the sources of the PMOS transistors being fixed at Vii, operates in a direct sensing mode when the transfer gates are off state, and then functions as a usual PMOS sense amplifier by turning on the transfer gates. Likewise for the NMOS sense amplifier.

公开(公告)号：US06185256B2

公开(公告)日：2001-02-06

申请号：US09062586

申请日：1998-04-20

申请人： Miyoshi Saito ,  Junji Ogawa

发明人： Miyoshi Saito ,  Junji Ogawa

IPC分类号： H04B330

CPC分类号： G11C7/1063 ,  G11C7/04 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/229 ,  H04L25/03878

摘要： A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when the signal transmission line is switched between the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched. This makes continuous readout possible and achieves an increase in the overall speed of the signal transmission system.

摘要翻译： 信号传输系统被构造为通过消除由前面的数据引入的符号间干扰成分，通过信号传输线路传输数据，而不需要为每一位预充电信号传输线。 信号传输线具有以分支结构或层次结构组织的多个可切换信号传输线，从多个信号传输线中的每一个连接至少一个读取数据的目标单元，以及读出电路，包括： 用于消除符号间干扰分量的电路连接到信号传输线，其中，符号间干扰成分消除电路减少了在多个信号传输线之间切换信号传输线时引入的噪声，从而提供平滑的符号间干扰成分消除操作 当信号传输线路被切换时。 这使连续读出成为可能，并实现了信号传输系统的整体速度的提高。

公开(公告)号：US6157688A

公开(公告)日：2000-12-05

申请号：US944516

申请日：1997-10-06

申请人： Hirotaka Tamura ,  Miyoshi Saito ,  Kohtaroh Gotoh ,  Shigetoshi Wakayama ,  Junji Ogawa ,  Hisakatsu Araki ,  Tsz-shing Cheung

发明人： Hirotaka Tamura ,  Miyoshi Saito ,  Kohtaroh Gotoh ,  Shigetoshi Wakayama ,  Junji Ogawa ,  Hisakatsu Araki ,  Tsz-shing Cheung

IPC分类号： G06F3/00 ,  G06F1/10 ,  G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H04B14/06 ,  G11C16/06

CPC分类号： H04L25/0276 ,  G06F13/4243 ,  H04L25/0278 ,  H04L25/0282 ,  H04L25/0288 ,  H04L25/497 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.