Prioritized handling of incoming packets by a network interface controller

    公开(公告)号:US10764194B2

    公开(公告)日:2020-09-01

    申请号:US15836869

    申请日:2017-12-10

    Abstract: A network interface controller includes a host interface, which is configured to be coupled to a host processor having a host memory. A network interface is configured to receive data packets from a network, each data packet including a header, which includes header fields, and a payload including data. Packet processing circuitry is configured to process one or more of the header fields and at least a part of the data and to select, responsively at least to the one or more of the header fields, a location in the host memory. The circuitry writes the data to the selected location and upon determining that the processed data satisfies a predefined criterion, asserts an interrupt on the host processor so as to cause the host processor to read the data from the selected location in the host memory.

    Application accelerator
    112.
    发明申请

    公开(公告)号:US20200014918A1

    公开(公告)日:2020-01-09

    申请号:US16291023

    申请日:2019-03-04

    Abstract: A system including an acceleration device including input circuitry configured, for each of a first plurality of video frames to be encoded, to receive an input including at least one raw video frame and at least one reference frame, and to divide each of the first plurality of video frames to be encoded into a second plurality of blocks, and similarity computation circuitry configured, for each one of the first plurality of video frame to be encoded: for each the block of the second plurality of blocks, to produce a score of result blocks based on similarity of each the block in each frame to be encoded to every block of the reference frame, and a displacement vector. Related apparatus and methods are also provided.

    In-node aggregation and disaggregation of MPI alltoall and alltoallv collectives

    公开(公告)号:US10521283B2

    公开(公告)日:2019-12-31

    申请号:US15446004

    申请日:2017-03-01

    Abstract: An MPI collective operation carried out in a fabric of network elements by transmitting MPI messages from all the initiator processes in an initiator node to designated ones of the responder processes in respective responder nodes. Respective payloads of the MPI messages are combined in a network interface device of the initiator node to form an aggregated MPI message. The aggregated MPI message is transmitted through the fabric to network interface devices of responder nodes, disaggregating the aggregated MPI message into individual messages, and distributing the individual messages to the designated responder node processes.

    Maintaining packet order in offload of packet processing functions

    公开(公告)号:US10382350B2

    公开(公告)日:2019-08-13

    申请号:US15701459

    申请日:2017-09-12

    Abstract: Network interface apparatus includes a host interface and a network interface, which receives packets in multiple packet flows destined for one or more virtual machines running on a host processor. Packet processing circuitry receives a first instruction from the host processor to offload preprocessing of the data packets in a specified flow in accordance with a specified rule, and initiates preprocessing of the data packets while writing one or more initial data packets from the specified flow to a temporary buffer. Upon subsequently receiving a second instruction to enable the specified rule, the initial data packets are delivered from the temporary buffer, after preprocessing by the packet processing circuitry, directly to a virtual machine to which the specified flow is destined, followed by preprocessing and delivery of subsequent data packets in the specified flow to the virtual machine.

    Network operation offloading for collective operations

    公开(公告)号:US10158702B2

    公开(公告)日:2018-12-18

    申请号:US14937907

    申请日:2015-11-11

    Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more work requests that are derived from an operation to be executed by the node. The NI maintains a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the work requests via the host interface, and to execute the work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

    In-node Aggregation and Disaggregation of MPI Alltoall and Alltoallv Collectives

    公开(公告)号:US20170255501A1

    公开(公告)日:2017-09-07

    申请号:US15446004

    申请日:2017-03-01

    Abstract: An MPI collective operation carried out in a fabric of network elements by transmitting MPI messages from all the initiator processes in an initiator node to designated ones of the responder processes in respective responder nodes. Respective payloads of the MPI messages are combined in a network interface device of the initiator node to form an aggregated MPI message. The aggregated MPI message is transmitted through the fabric to network interface devices of responder nodes, disaggregating the aggregated MPI message into individual messages, and distributing the individual messages to the designated responder node processes.

    Hardware-based congestion control for TCP traffic

    公开(公告)号:US20170093699A1

    公开(公告)日:2017-03-30

    申请号:US15278143

    申请日:2016-09-28

    CPC classification number: H04L69/16 H04L47/263 H04L47/28 H04L47/33 Y02D50/10

    Abstract: A method for congestion control includes receiving at a destination computer a packet transmitted on a given flow, in accordance with a predefined transport protocol, through a network by a transmitting network interface controller (NIC) of a source computer, and marked by an element in the network with a forward congestion notification. Upon receiving the marked packet in a receiving NIC of the destination computer, a congestion notification packet (CNP) indicating a flow to be throttled is immediately queued for transmission from the receiving NIC through the network to the source computer. Upon receiving the CNP in the transmitting NIC, transmission of further packets on at least the flow indicated by the CNP from the transmitting NIC to the network is immediately throttled, and an indication of the given flow is passed from the transmitting NIC to a protocol processing software stack running on the source computer.

    Network interface controller supporting network virtualization

    公开(公告)号:US09462047B2

    公开(公告)日:2016-10-04

    申请号:US14637414

    申请日:2015-03-04

    CPC classification number: H04L67/10 G06F9/45533 H04L12/4633 H04L45/64

    Abstract: A network interface device includes a host interface for connection to a host processor having a memory. A network interface is configured to transmit and receive data packets over a data network, which supports multiple tenant networks overlaid on the data network. Processing circuitry is configured to receive, via the host interface, a work item submitted by a virtual machine running on the host processor, and to identify, responsively to the work item, a tenant network over which the virtual machine is authorized to communicate, wherein the work item specifies a message to be sent to a tenant destination address. The processing circuitry generates, in response to the work item, a data packet containing an encapsulation header that is associated with the tenant network, and to transmit the data packet over the data network to at least one data network address corresponding to the specified tenant destination address.

    Sharing address translation between CPU and peripheral devices
    120.
    发明授权
    Sharing address translation between CPU and peripheral devices 有权
    共享CPU和外围设备之间的地址转换

    公开(公告)号:US09298642B2

    公开(公告)日:2016-03-29

    申请号:US13665946

    申请日:2012-11-01

    CPC classification number: G06F12/1081

    Abstract: A method for memory access includes maintaining in a host memory, under control of a host operating system running on a central processing unit (CPU), respective address translation tables for multiple processes executed by the CPU. Upon receiving, in a peripheral device, a work item that is associated with a given process, having a respective address translation table in the host memory, and specifies a virtual memory address, the peripheral device translates the virtual memory address into a physical memory address by accessing the respective address translation table of the given process in the host memory. The work item is executed in the peripheral device by accessing data at the physical memory address in the host memory.

    Abstract translation: 一种用于存储器访问的方法包括在主机操作系统在中央处理单元(CPU)上运行的主机操作系统的控制下维护主机存储器,用于由CPU执行的多个进程的各自的地址转换表。 在外围设备中接收与给定进程相关联的工作项,在主机存储器中具有相应的地址转换表,并指定虚拟存储器地址时,外围设备将虚拟存储器地址转换为物理存储器地址 通过访问主机存储器中给定进程的相应地址转换表。 通过访问主机存储器中的物理存储器地址上的数据,在外围设备中执行工作项。

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