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公开(公告)号：US20230034787A1
公开(公告)日：2023-02-02
申请号：US17885131
申请日：2022-08-10
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Mattia Boniardi , Mattia Robustelli
Abstract: Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of write operation to program one or more memory cells to a second state. Additionally or alternatively, a memory device may first attempt to use the first type of write operation to program one or more memory cells, and then may use the second type of write operation if the first attempt is unsuccessful.
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公开(公告)号：US20230019954A1
公开(公告)日：2023-01-19
申请号：US17875001
申请日：2022-07-27
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Anna Maria Conti , Innocenzo Tortorelli
Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.
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公开(公告)号：US20220415409A1
公开(公告)日：2022-12-29
申请号：US17361194
申请日：2021-06-28
Applicant: Micron Technology, Inc.
Inventor： Alessandro Sebastiani , Innocenzo Tortorelli
Abstract: Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A method may include writing memory cells to an intermediate state based on receiving a write command. Writing the intermediate state may include applying a first pulse having a first polarity to the memory cell. The method may include isolating a first access line coupled with the memory cell from a voltage source based on applying the first pulse. The method may also include applying a second pulse to a second access line coupled with the memory cell based on isolating the first access line.
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公开(公告)号：US20220190031A1
公开(公告)日：2022-06-16
申请号：US17119038
申请日：2020-12-11
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for a capacitive pillar architecture for a memory array are described. An access line within a memory array may be, include, or be coupled with a pillar. The pillar may include an exterior electrode, such as a hollow exterior electrode, surrounding an inner dielectric material that may further surround an interior, core electrode. The interior electrode may be maintained at a voltage level during at least a portion of an access operation for a memory cell coupled with the pillar. Such a pillar structure may increase a capacitance of the pillar, for example, based on a capacitive coupling between the interior and exterior electrodes. The increased capacitance may provide benefits associated with operating the memory array, such as increased memory cell programming speed, programming reliability, and read disturb immunity.
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公开(公告)号：US11342382B1
公开(公告)日：2022-05-24
申请号：US17119038
申请日：2020-12-11
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for a capacitive pillar architecture for a memory array are described. An access line within a memory array may be, include, or be coupled with a pillar. The pillar may include an exterior electrode, such as a hollow exterior electrode, surrounding an inner dielectric material that may further surround an interior, core electrode. The interior electrode may be maintained at a voltage level during at least a portion of an access operation for a memory cell coupled with the pillar. Such a pillar structure may increase a capacitance of the pillar, for example, based on a capacitive coupling between the interior and exterior electrodes. The increased capacitance may provide benefits associated with operating the memory array, such as increased memory cell programming speed, programming reliability, and read disturb immunity.
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Patent Agency Ranking
公开(公告)号：US20220036946A1
公开(公告)日：2022-02-03
申请号：US17399853
申请日：2021-08-11
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US20220013167A1
公开(公告)日：2022-01-13
申请号：US16926557
申请日：2020-07-10
Applicant: Micron Technology, Inc.
Inventor： Mattia Robustelli , Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano
Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.
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公开(公告)号：US20210407592A1
公开(公告)日：2021-12-30
申请号：US16959556
申请日：2019-12-03
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Innocenzo Tortorelli
Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.
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公开(公告)号：US20210272615A1
公开(公告)日：2021-09-02
申请号：US17325997
申请日：2021-05-20
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Anna Maria Conti , Mattia Robustelli , Innocenzo Tortorelli , Mario Allegra
IPC: G11C11/16
Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.
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公开(公告)号：US11094879B2
公开(公告)日：2021-08-17
申请号：US16121261
申请日：2018-09-04
Applicant: Micron Technology, Inc.
Inventor： Andrea Gotti , F. Daniel Gealy , Innocenzo Tortorelli , Enrico Varesi
Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements.
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