公开(公告)号：US11276454B2

公开(公告)日：2022-03-15

申请号：US16939669

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C16/34 ,  G11C11/406 ,  G11C11/4074 ,  G11C16/10 ,  G11C11/4072

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

公开(公告)号：US11257534B2

公开(公告)日：2022-02-22

申请号：US17076575

申请日：2020-10-21

Applicant: Micron Technology, Inc.

Inventor： Kristen M. Hopper ,  Debra M. Bell ,  Aaron P. Boehm

IPC: G11C11/24 ,  G11C11/22 ,  G11C11/4074 ,  G06F11/34 ,  G06F11/30 ,  G11C11/4076

Abstract: Methods, systems, and devices for a current monitor for a memory device are described. A memory device may monitor potential degradation of memory cells on the device by monitoring the amount of current drawn by one or more memory cells. As the memory cells degrade, the current supplied to the memory cells may change (e.g., increase due to additional leakage current. The memory device may indirectly monitor changes in the current supplied to the memory cells by monitoring a voltage of a node of a transistor that controls the amount of current supplied to the array of memory cells. The voltage at the control node may be compared to a reference voltage to determine whether the two voltages differ by a threshold amount, indicating that the memory cells are drawing more current. The memory device may output a status indicator when the voltages differ, for example, by the threshold amount.

公开(公告)号：US20220027066A1

公开(公告)日：2022-01-27

申请号：US17497212

申请日：2021-10-08

Applicant: Micron Technology, Inc.

Inventor： Rachael R. Carlson ,  Aparna U. Limaye ,  Diana C. Majerus ,  Debra M. Bell ,  Shea M. Morrison

IPC: G06F3/06 ,  G06F21/79 ,  G11C29/44 ,  G06F21/44 ,  H04L9/08

Abstract: Apparatuses and methods related to memory authentication. Memory devices can be authenticated utilizing authentication codes. An authentication code can be generated based on information stored in a fuse array of the memory device. The authentication code can be stored in the memory device. The stored authentication code can be compared to a captured authentication code based on fuse array information broadcast to memory components of the memory device. The authenticity of the memory device can be determined based on the comparison and can result in placing the memory device in an unlocked state.

公开(公告)号：US20210392269A1

公开(公告)日：2021-12-16

申请号：US16900330

申请日：2020-06-12

Applicant: Micron Technology, Inc.

Inventor： Zahra Hosseinimakarem ,  Debra M. Bell ,  Cheryl M. O'Donnell ,  Roya Baghi ,  Erica M. Gove

IPC: H04N5/232 ,  G01C19/5712

Abstract: Systems, apparatuses, and methods related to memory device sensors are described. Memory systems can include multiple types of memory devices including memory media and can write data to the memory media. Some types of memory devices include sensors embedded in the circuitry of the memory device that can generate data. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to another device. In an example, a method can include generating orientation data, including coordinates, of a memory device by measuring linear acceleration or rotational motion using a motion sensor embedded in circuitry of the memory device, receiving a signal that represents image data from an image sensor, and pairing the orientation data of the memory device with the image data.

公开(公告)号：US20210311822A1

公开(公告)日：2021-10-07

申请号：US17350099

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Aaron Jannusch ,  Brett K. Dodds ,  Debra M. Bell ,  Joshua E. Alzheimer ,  Scott E. Smith

IPC: G06F11/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

公开(公告)号：US11088153B2

公开(公告)日：2021-08-10

申请号：US16927717

申请日：2020-07-13

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell

IPC: H01L27/11 ,  G11C11/419 ,  G11C11/412 ,  H01L27/092

Abstract: Some embodiments include an integrated assembly having a first pull-down transistor, a second pull-down transistor, a first pull-up transistor and a second pull-up transistor. The first pull-down transistor has a first conductive-gate-body at a first level, and has an n-channel-device-active-region at a second level vertically offset from the first level. The first pull-up transistor has a second conductive-gate-body at the first level, and has a p-channel-device-active-region at the second level. The second pull-down transistor has a third conductive-gate-body at the second level, and has an n-channel-device-active-region at the first level. The second pull-up transistor has a fourth conductive-gate-body at the second level, and has a p-channel-device-active-region at the first level.

公开(公告)号：US20210173757A1

公开(公告)日：2021-06-10

申请号：US16707906

申请日：2019-12-09

Applicant: Micron Technology, Inc.

Inventor： Cheryl M. O'Donnell ,  Erica M. Gove ,  Zahra Hosseinimakarem ,  Debra M. Bell ,  Roya Baghi

IPC: G06F11/30 ,  G06F11/32 ,  G06F13/16

Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, another device can be coupled to a memory device with an embedded sensor. The memory device can transmit a signal representing sensor data generated by the embedded sensor using a sensor output coupled to the other device. A controller coupled to a memory device may determine one or more threshold values of a sensor or sensors embedded in a memory device. The memory device may transmit an indication responsive to one or more sensors detecting a value greater or less than a threshold and may transmit the indication to another device.

公开(公告)号：US20210165584A1

公开(公告)日：2021-06-03

申请号：US17148326

申请日：2021-01-13

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Naveh Malihi

IPC: G06F3/06 ,  G11C7/06

Abstract: Apparatuses and methods related to updating data lines for data generation in, for example, a memory device or a computing system that includes a memory device. Updating data lines can include updating a plurality of data lines. The plurality of data lines can provide data form the memory array responsive to a receipt of the access command. The plurality of data lines can also be updated responsive to a determination that an access command received at a memory device is unauthorized.

公开(公告)号：US20210097180A1

公开(公告)日：2021-04-01

申请号：US16586097

申请日：2019-09-27

Applicant: Micron Technology, Inc.

Inventor： Aparna U. Limaye ,  Diana C. Majerus ,  Rachael R. Carlson ,  Shea M. Morrison ,  Debra M. Bell

IPC: G06F21/56 ,  G06F3/06

Abstract: Apparatuses and methods related to detecting synchronization between multiple devices. The security of a device may be compromised if the device receives commands from unauthorized sources. A state of a device can be affected by the commands the device receives. A different device can determine whether there is synchronicity between device and the different device to determine whether the security of the device may have been compromised.

公开(公告)号：US20210064271A1

公开(公告)日：2021-03-04

申请号：US16553859

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Debra M. Bell ,  James S. Rehmeyer ,  Robert Bunnell ,  Nathaniel J. Meier

IPC: G06F3/06 ,  G11C17/16 ,  G11C17/18 ,  G11C11/4091 ,  G11C11/4072

Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells at intersections of memory rows and memory columns. The memory device further includes sense amplifiers corresponding to the memory rows. When the memory device powers on, the memory device writes one or more memory cells of the plurality of memory cells to a random data state before executing an access command received from a user, a memory controller, or a host device of the memory device. In some embodiments, to write the one or more memory cells, the memory device fires multiple memory rows at the same time without powering corresponding sense amplifiers such that data stored on memory cells of the multiple memory rows is overwritten and corrupted.