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    COMBINATION SCAN MANAGEMENT FOR BLOCK FAMILIES OF A MEMORY DEVICE
    111.
    发明申请
    COMBINATION SCAN MANAGEMENT FOR BLOCK FAMILIES OF A MEMORY DEVICE 有权

    公开(公告)号：US20220164105A1

    公开(公告)日：2022-05-26

    申请号：US17100709

    申请日：2020-11-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shane Nowell ,  Michael Sheperek ,  Larry J. Koudele ,  Vamsi Pavan Rayaprolu

    IPC: G06F3/06

    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.

    RELIABILITY SCAN ASSISTED VOLTAGE BIN SELECTION
    112.
    发明申请
    RELIABILITY SCAN ASSISTED VOLTAGE BIN SELECTION 有权

    公开(公告)号：US20220155956A1

    公开(公告)日：2022-05-19

    申请号：US17099546

    申请日：2020-11-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Vamsi Pavan Rayaprolu ,  Shane Nowell ,  Michael Sheperek

    IPC: G06F3/06

    Abstract: A system can include a memory device and a processing device to perform operations that include identifying voltage offset bins of the memory device, each of the first voltage offset bins satisfying a first age threshold criterion, identifying one or more second voltage offset bins of the memory device, each of the second voltage offset bins satisfying a second age threshold criterion, identifying a first block family associated with one of the first voltage offset bins, and performing a first scan of a first block of the first block family by: identifying, based on determined values of the first data state metric, a first identified voltage offset bin, and identifying one or more values of a second data state metric in scan metadata generated by a second scan, and identifying, based on the one or more values of the second data state metric, a second identified voltage offset bin.

    DETERMINATION OF STATE METRICS OF MEMORY SUB-SYSTEMS FOLLOWING POWER EVENTS
    115.
    发明申请
    DETERMINATION OF STATE METRICS OF MEMORY SUB-SYSTEMS FOLLOWING POWER EVENTS 有权

    公开(公告)号：US20220059181A1

    公开(公告)日：2022-02-24

    申请号：US17301348

    申请日：2021-03-31

    Applicant: Micron Technology, Inc.

    Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Steven Michael Kientz

    IPC: G11C29/44 ,  G11C29/42 ,  G11C29/12

    Abstract: Disclosed is a system including a memory device having a plurality of physical cells and a processing device, operatively coupled with the memory device, to perform operations that include selecting, responsive to detecting a power event, a subset of a plurality of memory cells of the memory device, the memory device being characterized by auxiliary read metadata identifying one or more read offsets for each of the plurality of memory cells, the one or more read offsets representing corrections to read signals applied to the respective memory cell during a read operation. The operations further include performing one or more diagnostic read operations for each of the subset of the plurality of memory cells of the memory device and modifying the auxiliary read metadata by updating the one or more read offsets for at least some of the plurality of memory cells of the memory device.

    OPEN BLOCK FAMILY DURATION LIMITED BY TIME AND TEMPERATURE
    116.
    发明申请
    OPEN BLOCK FAMILY DURATION LIMITED BY TIME AND TEMPERATURE 有权

    公开(公告)号：US20220057934A1

    公开(公告)日：2022-02-24

    申请号：US16947819

    申请日：2020-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen ,  Steven Michael Kientz ,  Kishore Kumar Muchherla

    IPC: G06F3/06 ,  G06F1/324 ,  G06F1/3228 ,  G01K3/04

    Abstract: A includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to: initialize a block family associated with the memory device; initialize a timer at initialization of the block family; and aggregate temperature values received from sensor(s) of the memory device over time to generate an aggregate temperature. Responsive to programming a page residing on the memory device, the processing device associates the page with the block family. The processing device closes the block family in response to the aggregate temperature being greater than a first temperature value and the timer reaching a first time value. The processing device closes the block family in response to the aggregate temperature being less than or equal to the first temperature value and the timer reaching a second time value that is greater than the first time value.

    Bin placement according to program-erase cycles
    119.
    发明授权
    Bin placement according to program-erase cycles 有权

    公开(公告)号：US11217320B1

    公开(公告)日：2022-01-04

    申请号：US16948688

    申请日：2020-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Michael Sheperek ,  Mustafa N. Kaynak ,  Steven Michael Kientz

    IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/32 ,  G11C16/14

    Abstract: A system includes a memory device having a plurality of dice and A processing device to perform operations, including determining a representative number of program-erase cycles performed across the plurality of dice. The operations further include tracking the representative number of program-erase cycles over time. The operations further include, in response to the representative number of program-erase cycles satisfying a first threshold criterion, adding an additional threshold voltage offset bin to a plurality of threshold voltage offset bins for the memory device, wherein each of the plurality of threshold voltage offset bins comprises a corresponding window of time after program of data to the memory device.

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