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    Package-on-package semiconductor assemblies and methods of manufacturing the same
    111.
    发明授权
    Package-on-package semiconductor assemblies and methods of manufacturing the same 有权

    公开(公告)号：US11139229B2

    公开(公告)日：2021-10-05

    申请号：US16536490

    申请日：2019-08-09

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Jack E. Murray

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

    Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

    FABRICATED TWO-SIDED MILLIMETER WAVE ANTENNA USING THROUGH-SILICON-VIAS
    112.
    发明申请
    FABRICATED TWO-SIDED MILLIMETER WAVE ANTENNA USING THROUGH-SILICON-VIAS 有权

    公开(公告)号：US20210280538A1

    公开(公告)日：2021-09-09

    申请号：US17328134

    申请日：2021-05-24

    Applicant: Micron Technology, Inc.

    Inventor： John F. Kaeding ,  Owen R. Fay

    IPC: H01L23/66 ,  H01Q1/22 ,  H01L23/00 ,  H01L27/108 ,  H01L25/065 ,  H01L23/538

    Abstract: A system may include a first semiconductor substrate having a first side and a second side opposite the first side. The system may further include multiple device layers positioned on the first side of the substrate. The system may also include a first portion of an antenna structure positioned within at least one of the multiple device layers. The system may include a second portion of the antenna structure positioned over the second side of the substrate. The system may further include a via passing through the substrate and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.

    High density pillar interconnect conversion with stack to substrate connection
    113.
    发明授权
    High density pillar interconnect conversion with stack to substrate connection 有权

    公开(公告)号：US11088114B2

    公开(公告)日：2021-08-10

    申请号：US16671546

    申请日：2019-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

    IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/60

    Abstract: A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.

    Interconnect structures for preventing solder bridging, and associated systems and methods
    117.
    发明授权
    Interconnect structures for preventing solder bridging, and associated systems and methods 有权

    公开(公告)号：US10600750B2

    公开(公告)日：2020-03-24

    申请号：US16182924

    申请日：2018-11-07

    Applicant: Micron Technology, Inc.

    Inventor： Kyle S. Mayer ,  Owen R. Fay

    IPC: H01L23/00 ,  H01L21/288

    Abstract: Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

    Tunable integrated millimeter wave antenna using laser ablation and/or fuses
    119.
    发明申请
    Tunable integrated millimeter wave antenna using laser ablation and/or fuses 审中-公开

    公开(公告)号：US20200036093A1

    公开(公告)日：2020-01-30

    申请号：US16045562

    申请日：2018-07-25

    Applicant: Micron Technology, Inc.

    Inventor： John F. Kaeding ,  Owen R. Fay

    IPC: H01Q1/48

    Abstract: A method for tuning an antenna may include depositing multiple portions of an antenna structure onto a substrate. The method may further include electrically coupling each of the portions of the antenna structure. The method may also include severing an electrical connection between two of the portions of the antenna structure to tune the antenna structure for use with a transmission device.

    Semiconductor device assembly with pillar array
    120.
    发明授权
    Semiconductor device assembly with pillar array 有权

    公开(公告)号：US10529592B2

    公开(公告)日：2020-01-07

    申请号：US15830839

    申请日：2017-12-04

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Akshay N. Singh ,  Kyle K. Kirby

    IPC: H01L21/48 ,  H01L21/66 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065

    Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.

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