公开(公告)号：US11797229B2

公开(公告)日：2023-10-24

申请号：US17360943

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F3/06 ,  G06F1/04 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F1/04 ,  G06F13/1689 ,  G06F2213/16

Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.

公开(公告)号：US11777767B2

公开(公告)日：2023-10-03

申请号：US17874939

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: H04L25/03

CPC classification number: H04L25/03057

Abstract: Methods, systems, and devices for techniques for time-variable decision feedback equalization are described. A memory device may be coupled with a host device using one or more conductive lines. A receiver may receive a signal transmitted from another device over a conductive line. The receiver may include a decision circuit used to determine voltages of the received signal based on the received signal and a feedback signal and output an output signal. The receiver may include a variable time-delay circuit configured to output delayed signals that are delayed versions of the output signal and a gain circuit that is configured to scale the delayed signals to generate the feedback signal. The variable time-delay circuit may include delay elements having variable delay parameters. The receiver may be coupled with a memory array that stores the information conveyed by the output signal.

公开(公告)号：US20230116891A1

公开(公告)日：2023-04-13

申请号：US17499025

申请日：2021-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis

IPC: G11C11/406 ,  G11C7/10 ,  G11C29/42

Abstract: A semiconductor device may implement a command-over-data function on a multi-level signaling data bus architectures. The multi-level signaling data bus architecture may support a multi-level communication architecture that includes a plurality of channels each including conversion of M bitstreams to N multi-level signals, where M is greater than N. A bitstream includes a plurality of bits provided serially, with each bit of the bitstream provided over a period of time. The multi-level signaling data bus is adapted to transmit data using a first set of assigned states of the data bus, and to transmit commands using at least a second assigned state of the data bus.

公开(公告)号：US11621038B2

公开(公告)日：2023-04-04

申请号：US17381860

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Shindeok Kang ,  Timothy M. Hollis ,  Dragos Dimitriu

IPC: G11C11/56 ,  G11C7/02 ,  G11C5/14 ,  G11C7/24

Abstract: Methods, systems, and devices related to an improved driver for non-binary signaling are described. A driver for a signal line may include a set of drivers of a first type and a set of drivers of a second type. When the driver drives the signal line using multiple drivers of the first type, at least one additional driver of the first type may compensate for non-linearities associated with one or more other drivers of the first type, which may have been calibrated at other voltages. The at least one additional driver of the first type may be calibrated for use at a particular voltage, to compensate for non-linearities associated with the one or more other drivers of the first type as exhibited at that particular voltage.

公开(公告)号：US20230004507A1

公开(公告)日：2023-01-05

申请号：US17864023

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F13/16 ,  G06F13/40 ,  G11C5/06 ,  G11C5/02 ,  G06F13/42 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4096 ,  G11C5/04

Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

公开(公告)号：US11502881B2

公开(公告)日：2022-11-15

申请号：US17229092

申请日：2021-04-13

Applicant: Micron Technology, Inc.

Inventor： Feng Lin ,  Timothy M. Hollis

IPC: H04L25/49 ,  G11C7/20 ,  H04L25/03 ,  H04L7/00 ,  G11C7/10

Abstract: A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

公开(公告)号：US20220346220A1

公开(公告)日：2022-10-27

申请号：US17238797

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： M. Ataul Karim ,  David K. Ovard ,  Aparna U. Limaye ,  Timothy M. Hollis

IPC: H05K1/02 ,  H04B3/487 ,  H04B3/32

Abstract: Methods, systems, and devices for crosstalk cancellation for signal lines are described. In some examples, a device (e.g., a host device or a memory device) may generate a first signal and may invert the first signal to obtain an inverted first signal. The device may obtain a second signal based on attenuating a first range of frequencies of the inverted first signal and a second range of frequencies of the inverted first signal, where the first range of frequencies is below a first threshold frequency and the second range of frequencies is above a second threshold frequency that is greater than the first threshold frequency. The device may transmit the first signal via a first signal line of a set of signal lines and the second signal line via a second signal line of the set of signal lines.

公开(公告)号：US11418370B2

公开(公告)日：2022-08-16

申请号：US17149364

申请日：2021-01-14

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: H04L25/03

Abstract: Methods, systems, and devices for techniques for time-variable decision feedback equalization are described. A memory device may be coupled with a host device using one or more conductive lines. A receiver may receive a signal transmitted from another device over a conductive line. The receiver may include a decision circuit used to determine voltages of the received signal based on the received signal and a feedback signal and output an output signal. The receiver may include a variable time-delay circuit configured to output delayed signals that are delayed versions of the output signal and a gain circuit that is configured to scale the delayed signals to generate the feedback signal. The variable time-delay circuit may include delay elements having variable delay parameters. The receiver may be coupled with a memory array that stores the information conveyed by the output signal.

公开(公告)号：US20220028448A1

公开(公告)日：2022-01-27

申请号：US16940194

申请日：2020-07-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： M. Ataul Karim ,  Timothy M. Hollis

IPC: G11C11/4093 ,  G11C11/56 ,  H04L27/08

Abstract: Apparatuses, systems, and methods for high-pass filtering pre-emphasis circuits. A device may use a pre-emphasis driver to provide a multi-level signal based on multiple binary signals. The pre-emphasis driver includes a primary driver coupled in parallel with at least one equalizer path, each of which includes an equalizer driver and a filtering element. The filtering element may be an AC filtering element, such as a capacitor. The equalizer paths may contribute equalized signal(s) which have a high-pass filtering behavior. The pre-emphasis circuit may combine the primary signal from the primary driver and the equalized signals to generate an overall output multi-level signal. In some embodiments, the pre-emphasis driver may be a pulse amplitude modulated (PAM) driver, such as a PAM4 driver with four levels of the multi-level driver.

公开(公告)号：US20220005515A1

公开(公告)日：2022-01-06

申请号：US17360964

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G11C8/18 ,  G11C8/06 ,  G11C7/10 ,  G11C7/22

Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.