公开(公告)号：US06297535B1

公开(公告)日：2001-10-02

申请号：US09510096

申请日：2000-02-22

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr.

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr.

IPC分类号： H01L31119

CPC分类号： H01L29/66659 ,  H01L21/28176 ,  H01L21/28194 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S257/90 ,  Y10S438/91

摘要： A transistor fabrication process is provided which derives a benefit from having barrier atoms incorporated in a lateral area under a gate oxide of the transistor in close proximity to the drain. To form the transistor, a gate oxide layer is first grown across a silicon-based substrate. A polysilicon layer is then deposited across the gate oxide layer. Portions of the polysilicon layer and the oxide layer are removed to form a gate conductor and gate oxide, thereby exposing source-side and drain-side junctions within the substrate. An LDD implant is performed to lightly dope the source-side and drain-side junctions. An etch stop material may be formed upon opposed sidewall surfaces of the gate conductor, the upper surface of the gate conductor, and the source-side and drain-side junctions. Spacers may then be formed laterally adjacent the etch stop material located upon sidewall surfaces of the gate conductor. The unmasked portions of the source-side and drain-side junctions are heavily doped, resulting in source and drain regions that are aligned to the exposed lateral edges of the spacers. The drain-side spacer is removed and barrier atoms are forwarded through the exposed etch stop material and into a substrate/gate oxide interface region near the drain junction. The barrier atoms help reduce hot electron effects by blocking diffusion avenues of carriers (holes or electrons) from the drain-side junction into the gate oxide.

摘要翻译： 提供了一种晶体管制造工艺，该方法得益于将栅极原子结合在晶体管的栅极氧化物附近在漏极附近的优点。 为了形成晶体管，首先在硅基衬底上生长栅氧化层。 然后在栅极氧化物层上沉积多晶硅层。 去除多晶硅层和氧化物层的部分以形成栅极导体和栅极氧化物，从而暴露衬底内的源极侧和漏极侧结。 进行LDD注入以轻轻地掺杂源极侧漏极和漏极侧结。 蚀刻停止材料可以形成在栅极导体的相对的侧壁表面，栅极导体的上表面以及源极侧和漏极侧结。 然后可以在位于栅极导体的侧壁表面上的蚀刻停止材料的横向邻近地形成间隔。 源侧和漏极侧结的未屏蔽部分被重掺杂，导致源极和漏极区域与间隔物的暴露的侧向边缘对准。 去除漏极侧隔离物，并且阻挡原子通过暴露的蚀刻停止材料并且进入到漏极结附近的衬底/栅极氧化物界面区域中。 阻挡原子有助于通过阻止载流子（空穴或电子）从漏极侧结到扩散通道到栅极氧化物中来减少热电子效应。

公开(公告)号：US06274442B1

公开(公告)日：2001-08-14

申请号：US09116417

申请日：1998-07-15

申请人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford, Jr. ,  Charles E. May

IPC分类号： H01L21336

CPC分类号： H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： An integrated circuit fabrication process is provided for incorporating barrier atoms, preferably nitrogen atoms, within a barrier layer. The barrier layer is interposed between the gate dielectric and the semiconductor substrate. The barrier layer serves to inhibit the passage of dopants from the gate conductor into the channel area. The barrier layer is preferably a nitrogen doped silicon epitaxial layer. The barrier layer may be composed of two layers, a silicon epitaxial layer and a nitrogen doped epitaxial layer formed upon the silicon epitaxial layer.

摘要翻译： 提供集成电路制造方法，用于在屏障层内并入屏障原子，优选氮原子。 阻挡层介于栅电介质和半导体衬底之间。 阻挡层用于抑制掺杂剂从栅极导体进入沟道区的过程。 阻挡层优选为氮掺杂硅外延层。 阻挡层可以由两层构成，硅外延层和形成在硅外延层上的氮掺杂外延层。

公开(公告)号：US06261909B1

公开(公告)日：2001-07-17

申请号：US09225389

申请日：1999-01-05

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L29/66613 ,  H01L29/7834

摘要： The present invention is directed to a method of forming a transistor having very shallow junctions and a reduced channel length, and a transistor incorporating same. In general, the method comprises forming a first process layer above a semiconducting substrate, and forming a second process layer comprised of an oxidation resistant material above the first process layer. The method continues with the formation of an opening in the first and second process layers and oxidation of the substrate lying within the opening to form a third process layer. Next, a second opening is formed in the third process layer, and a plurality of sidewall spacers are formed in the second opening. The method concludes with the formation of a gate dielectric above the substrate and between the sidewall spacers, the formation of a gate conductor above the gate dielectric, and the formation of a plurality of source and drain regions in the substrate. The transistor is comprised of a recess formed in the substrate, a gate dielectric positioned above the substrate lying within the recess, the interface between said gate dielectric and said substrate being positioned beneath the surface of said substrate. The transistor further comprises a gate conductor positioned above the gate dielectric, a plurality of sidewall spacers positioned adjacent the gate conductor, and a plurality of source/drain regions formed in the substrate.

摘要翻译： 本发明涉及一种形成具有非常浅的结和减小的沟道长度的晶体管的方法，以及并入其的晶体管。 通常，该方法包括在半导体衬底上形成第一工艺层，以及形成由第一工艺层上方的耐氧化材料构成的第二工艺层。 该方法继续在第一和第二处理层中形成开口并且位于开口内的基板的氧化以形成第三处理层。 接下来，在第三处理层中形成第二开口，并且在第二开口中形成多个侧壁间隔物。 该方法的结论是在衬底之上和侧壁间隔物之间​​形成栅极电介质，在栅极电介质上形成栅极导体，以及在衬底中形成多个源极和漏极区域。 晶体管由形成在基板中的凹槽，位于凹槽内的基板上方的栅介质构成，所述栅极电介质和所述基板之间的界面位于所述基板的表面之下。 晶体管还包括位于栅极电介质上方的栅极导体，邻近栅极导体定位的多个侧壁间隔件，以及形成在基板中的多个源极/漏极区域。

公开(公告)号：US06259142B1

公开(公告)日：2001-07-10

申请号：US09056837

申请日：1998-04-07

申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L2976

CPC分类号： H01L29/66484 ,  H01L29/7831

摘要： A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another by means of a gate insulating layer that is formed adjacent the side-walls of each firs gate electrode. Source and drain regions are formed adjacent the ends of the multiple split gate to define a channel region.

摘要翻译： 具有多个分割栅极的半导体集成电路使用第一多晶硅层和第二多晶硅层形成，以在有源区内形成交替的第一和第二栅电极。 交替的栅电极通过与每个第一栅电极的侧壁相邻形成的栅极绝缘层彼此电隔离。 源极和漏极区域形成在多分裂栅极的端部附近以限定沟道区域。

公开(公告)号：US06245638B1

公开(公告)日：2001-06-12

申请号：US09128235

申请日：1998-08-03

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Charles E. May

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  Y10S148/05

摘要： Semiconductor device fabrication techniques which integrate the formation of trench isolation areas and gate insulating layers are provided. The fabrication techniques include forming one or more sacrificial layers, such as nitrided oxide layers, over regions of the substrate adjacent to a trench isolation region. The sacrificial layers are then removed prior to gate insulating layer formation. The formation of the sacrificial layers improves the trench structure and also improves the substrate surface for the subsequent formation of the gate insulating layer and gate electrode.

摘要翻译： 提供集成沟槽隔离区域和栅极绝缘层的形成的半导体器件制造技术。 制造技术包括在与沟槽隔离区相邻的衬底的区域上形成一个或多个牺牲层，例如氮化氧化物层。 然后在形成栅极绝缘层之前去除牺牲层。 牺牲层的形成改善了沟槽结构，并且还改善了衬底表面，以便随后形成栅极绝缘层和栅电极。

公开(公告)号：US06239476B1

公开(公告)日：2001-05-29

申请号：US09176132

申请日：1998-10-21

申请人： Mark I. Gardner ,  Thomas E. Spikes, Jr. ,  H. Jim Fulford, Jr.

发明人： Mark I. Gardner ,  Thomas E. Spikes, Jr. ,  H. Jim Fulford, Jr.

IPC分类号： H01L2900

CPC分类号： H01L21/76224

摘要： A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A trench surface boundary is defined where the trench sidewalls intersect the upper surface of the semiconductor substrate. The trench may be filled with a trench fill material. A protective layer is then formed above the trench. The protective layer covers the trench and laterally extends above the semiconductor substrate at least a first distance beyond the trench surface boundaries.

摘要翻译： 提出了一种用于制造集成电路的方法，其中在半导体衬底的场区域中对沟槽进行构图。 沟槽通过沟槽底板和沟槽侧壁限定在半导体衬底的内部。 限定沟槽表面边界，其中沟槽侧壁与半导体衬底的上表面相交。 沟槽可以填充沟槽填充材料。 然后在沟槽上方形成保护层。 保护层覆盖沟槽并横向延伸超过沟槽表面边界至少第一距离半导体衬底上方。

公开(公告)号：US06218720B1

公开(公告)日：2001-04-17

申请号：US09176131

申请日：1998-10-21

申请人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford, Jr.

发明人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford, Jr.

IPC分类号： H01L2900

CPC分类号： H01L21/76224 ,  H01L21/3145 ,  H01L21/3185

摘要： A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A liner that primarily comprises nitride is formed upon the trench floor and sidewalls. The liner is then oxidized. A trench dielectric may be formed within the trench and planarized to complete the isolation structure.

摘要翻译： 提出了一种用于制造集成电路的方法，其中在半导体衬底的场区域中对沟槽进行构图。 沟槽通过沟槽底板和沟槽侧壁限定在半导体衬底的内部。 主要包括氮化物的衬垫形成在沟槽底板和侧壁上。 然后将衬里氧化。 沟槽电介质可以形成在沟槽内并且被平坦化以完成隔离结构。

公开(公告)号：US06207995B1

公开(公告)日：2001-03-27

申请号：US09255917

申请日：1999-02-23

申请人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford

发明人： Mark I. Gardner ,  Dim-Lee Kwong ,  H. Jim Fulford

IPC分类号： H01L2976

CPC分类号： H01L21/28194 ,  H01L29/42368 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/78391

摘要： An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate insulating layer on the substrate with a first outwardly tapered sidewall and a second outwardly tapered sidewall. A gate electrode is formed on the gate insulating layer. A first source/drain region and a second source/drain region are formed in the substrate by implanting ions into the substrate, wherein a first portion of the ions passes through the first sidewall and a second portion of the ions passes through the second sidewall. The method provides for incorporation of spacer-like structure into a gate dielectric layer. Conventional spacer fabrication may be eliminated and graded source/drain regions established with a single implant.

摘要翻译： 提供集成电路及其制造晶体管的方法。 在一个方面，该方法包括以下步骤：在衬底上形成具有第一向外锥形侧壁和第二向外渐缩侧壁的栅极绝缘层。 在栅极绝缘层上形成栅电极。 通过将离子注入衬底而在衬底中形成第一源/漏区和第二源极/漏极区，其中离子的第一部分穿过第一侧壁，并且离子的第二部分通过第二侧壁。 该方法提供了将间隔物结构结合到栅介质层中。 可以消除传统的间隔物制造，并用单个植入物建立分级的源极/漏极区域。

公开(公告)号：US06204148B1

公开(公告)日：2001-03-20

申请号：US09329843

申请日：1999-06-11

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

IPC分类号： H01L2176

CPC分类号： H01L29/66583

摘要： A partially formed semiconductor device includes a substrate, a first layer, a layer of polysilicon, and a grown layer of polysilicon. The first layer is positioned above at least a portion of the substrate. The layer of polysilicon is positioned above at least a portion of the first layer and has a first opening formed therein. The first opening has a first width that is defined by a plurality of sidewalls. The grown layer of polysilicon is positioned adjacent at least the plurality of sidewalls and the grown layer of polysilicon defines a second opening. The second opening has a second width with the second width being less than the first width. A method for partially forming a semiconductor device includes forming a process layer above at least a portion of a substrate. A layer of polysilicon is formed above at least a portion of the process layer. An opening is formed in the layer of polysilicon, and the opening has a first width that is defined by a plurality of sidewalls. The first width of the opening is reduced to a second width by growing a layer of polysilicon adjacent at least a portion of the sidewalls of the opening.

摘要翻译： 部分形成的半导体器件包括衬底，第一层，多晶硅层和生长的多晶硅层。 第一层位于衬底的至少一部分上方。 多晶硅层位于第一层的至少一部分的上方，并且其中形成有第一开口。 第一开口具有由多个侧壁限定的第一宽度。 多晶硅生长层位于至少多个侧壁附近，并且生长的多晶硅层限定第二开口。 第二开口具有第二宽度，第二宽度小于第一宽度。 部分形成半导体器件的方法包括在衬底的至少一部分上方形成工艺层。 在工艺层的至少一部分上方形成多晶硅层。 在多晶硅层中形成开口，并且开口具有由多个侧壁限定的第一宽度。 通过在开口的侧壁的至少一部分附近生长一层多晶硅，将开口的第一宽度减小到第二宽度。

公开(公告)号：US06201278B1

公开(公告)日：2001-03-13

申请号：US09028896

申请日：1998-02-24

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L31062

CPC分类号： H01L29/7834 ,  H01L29/66621

摘要： An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.

摘要翻译： 公开了一种具有栅电极和沟槽中的绝缘间隔物的IGFET。 IGFET包括具有相对侧壁的沟槽和半导体衬底中的底表面，底表面上的栅极绝缘体，栅极绝缘体上的栅极电极以及栅电极和侧壁之间的绝缘间隔物。 形成IGFET的方法包括将掺杂层注入到衬底中，通过掺杂层完全蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分为源极和漏极区，将绝缘隔离材料的覆盖层沉积在 基板并施加各向异性蚀刻以在侧壁上形成绝缘间隔物，在绝缘隔离物之间的底表面的中心部分上生长栅极绝缘体，在栅极绝缘体上沉积栅电极材料和绝缘间隔物，抛光栅极 电极材料，使得栅电极基本上与衬底的顶表面对准，并施加高温退火以扩散底表面下面的源极和漏极区域，从而形成源极和漏极，其通道结基本上与 栅电极。 有利地，沟道长度明显小于沟槽长度。