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1.发明授权Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance 有权具有良好的界面性能的超薄高K栅极电介质，可提高半导体器件的性能公开(公告)号：US06911707B2
公开(公告)日：2005-06-28
申请号：US09207972
申请日：1998-12-09
IPC分类号： H01L21/28 , H01L21/314 , H01L29/51 , H01L29/76
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3144 , H01L29/513 , H01L29/517 , H01L29/518
摘要： An ultrathin gate dielectric having a graded dielectric constant and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A thin nitrogen-containing oxide, preferably having a thickness of less than about 10 angstroms, is formed on a semiconductor substrate. A silicon nitride layer having a thickness of less than about 30 angstroms may be formed over the nitrogen-containing oxide. The oxide and nitride layers are annealed in ammonia and nitrous oxide ambients, and the nitride layer thickness is reduced using a flowing-gas etch process. The resulting two-layer gate dielectric is believed to provide increased capacitance as compared to a silicon dioxide dielectric while maintaining favorable interface properties with the underlying substrate. In an alternative embodiment, a different high dielectric constant material is substituted for the silicon nitride. Alternatively, both nitride and a different high dielectric constant material may be used so that a three-layer dielectric is formed.
摘要翻译： 提供具有渐变介电常数的超薄栅极电介质及其形成方法。 认为栅极电介质允许包括晶体管和双栅极存储器单元的半导体器件的增强的性能。 在半导体衬底上形成薄的含氮氧化物，优选具有小于约10埃的厚度。 可以在含氮氧化物上形成厚度小于约30埃的氮化硅层。 氧化物和氮化物层在氨和一氧化二氮环境中退火，并且使用流动气体蚀刻工艺来减少氮化物层的厚度。 与二氧化硅电介质相比，所得到的双层栅极电介质被认为提供增加的电容，同时保持与底层衬底的有利的界面性质。 在替代实施例中，用不同的高介电常数材料代替氮化硅。 或者，可以使用氮化物和不同的高介电常数材料，从而形成三层电介质。
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2.发明授权公开(公告)号：US06218720B1
公开(公告)日：2001-04-17
申请号：US09176131
申请日：1998-10-21
IPC分类号： H01L2900
CPC分类号： H01L21/76224 , H01L21/3145 , H01L21/3185
摘要： A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A liner that primarily comprises nitride is formed upon the trench floor and sidewalls. The liner is then oxidized. A trench dielectric may be formed within the trench and planarized to complete the isolation structure.
摘要翻译： 提出了一种用于制造集成电路的方法，其中在半导体衬底的场区域中对沟槽进行构图。 沟槽通过沟槽底板和沟槽侧壁限定在半导体衬底的内部。 主要包括氮化物的衬垫形成在沟槽底板和侧壁上。 然后将衬里氧化。 沟槽电介质可以形成在沟槽内并且被平坦化以完成隔离结构。
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3.发明授权公开(公告)号：US06552776B1
公开(公告)日：2003-04-22
申请号：US09183176
申请日：1998-10-30
申请人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
发明人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
IPC分类号： G03B2754
CPC分类号： G03F7/70558 , G03F7/70191 , G03F7/706
摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.
摘要翻译： 公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。 光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。 以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。 这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。 结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。 优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化 数据以提供所需的光强度变化。 本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。
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4.发明授权Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer 有权使用牺牲多晶硅种子层形成超薄栅极电介质的先进制造技术公开(公告)号：US06531364B1
公开(公告)日：2003-03-11
申请号：US09129703
申请日：1998-08-05
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/28211 , H01L29/513 , H01L29/518
摘要： A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. As an option, the sacrificial polysilicon layer may be heated such that it is recrystallized. The sacrificial polysilicon layer is preferably annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Polysilicon may be deposited upon the gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. LDD and source/drain areas may be formed adjacent to the gate conductor.
摘要翻译： 提出了一种用于形成晶体管的方法，其中多晶硅优选沉积在介电覆盖的衬底上以形成牺牲多晶硅层。 然后可以将牺牲多晶硅层还原成所需的厚度。 牺牲多晶硅层的厚度减少优选通过氧化牺牲多晶硅层的一部分然后蚀刻氧化部分进行。 作为选择，可以加热牺牲多晶硅层使其重结晶。 牺牲多晶硅层优选在含氮环境中退火，使得其被转换成包括氮化物的栅极电介质层。 多晶硅可以沉积在栅极介电层上，并且可以去除多晶硅的部分以形成栅极导体。 LDD和源极/漏极区域可以形成在栅极导体附近。
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5.发明授权Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures 有权具有低电阻金属源和漏极的绝缘隔离晶体管，使用牺牲源极和漏极结构形成公开(公告)号：US06303962B1
公开(公告)日：2001-10-16
申请号：US09227512
申请日：1999-01-06
IPC分类号： A01L2701
CPC分类号： H01L29/66757 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/78675
摘要： A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The transistor channel is located in a polysilicon layer arranged over a dielectric layer on a semiconductor substrate. To fabricate the transistor, an isolating dielectric, polysilicon layer, and protective dielectric layer are deposited over a semiconductor substrate. Source/drain trenches are formed in the protective dielectric and polysilicon layers and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which may be formed from a low-resistance metal. The resulting transistor may exhibit low contact and series resistances, and increased operation speed.
摘要翻译： 在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻源极和漏极区域提供并形成晶体管。 晶体管的栅极也可以由诸如金属的低电阻材料形成。 晶体管沟道位于布置在半导体衬底上的电介质层上的多晶硅层中。 为了制造晶体管，在半导体衬底上沉积隔离电介质，多晶硅层和保护电介质层。 源极/漏极沟槽形成在保护电介质层和多晶硅层中，随后填充有牺牲电介质。 位于这些牺牲电介质之间的保护电介质被去除，并被替代为可由低电阻金属形成的侧壁间隔物，栅极电介质和栅极导体。 随后去除牺牲电介质并用可由低电阻金属形成的源极/漏极区域代替。 所得到的晶体管可以表现出低接触和串联电阻，并且增加了操作速度。
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6.发明授权Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit 有权在集成电路中分别优化了n沟道和p沟道晶体管的栅极结构公开(公告)号：US06255698B1
公开(公告)日：2001-07-03
申请号：US09301263
申请日：1999-04-28
IPC分类号： H01L2976
CPC分类号： H01L21/823842 , H01L29/66545
摘要： An integrated circuit containing separately optimized gate structures for n-channel and p-channel transistors is provided and formed. Original gate structures for both n-channel and p-channel transistors are patterned over appropriately-doped active regions of a semiconductor substrate. Protective dielectrics are formed over the semiconductor substrate to the same elevation level as the upper surfaces of the original gate structures, so that only the upper surfaces of the gate structures are exposed. A masking layer is used to cover the gate structures of either the p-channel or the n-channel transistors. The uncovered gate structures are removed, forming a trench within the protective dielectric in place of each removed gate structure. The trenches are refilled with a new gate structure which is preferably optimized for operation of the appropriate transistor type (n-channel or p-channel).
摘要翻译： 提供并形成了包含用于n沟道和p沟道晶体管的单独优化的栅极结构的集成电路。 用于n沟道和p沟道晶体管的原始栅极结构在半导体衬底的适当掺杂的有源区上被图案化。 在半导体衬底上形成与原始栅极结构的上表面相同的高度水平面的保护电介质，使得只有栅极结构的上表面露出。 掩模层用于覆盖p沟道或n沟道晶体管的栅极结构。 去除未覆盖的栅极结构，在保护电介质内形成沟槽，代替每个去除的栅极结构。 沟槽用新的栅极结构重新填充，该栅极结构优选地适合于适当的晶体管类型（n沟道或p沟道）的操作。
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7.发明授权Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate 失效具有从硅基底层隔离的低K介电材料的沟槽隔离结构
公开(公告)号：US6140691A
公开(公告)日：2000-10-31
申请号：US994701
申请日：1997-12-19
IPC分类号： H01L21/762 , H01L29/00 , H01L23/58 , H01L29/76 , H01L29/94
CPC分类号： H01L21/76224
摘要： A trench isolation structure is provided which includes a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active areas separated by the trench isolation structure, being directly proportional to K, is thus reduced. As a result, the lateral width of the isolation structure may be decreased without significantly increasing the capacitance between those active areas. In an embodiment, a fabrication process for the trench isolation structure may include a trench is etched within a semiconductor substrate upon which a masking layer is formed. An oxide liner is thermally grown upon the sidewalls and base of the trench. A layer of low K dielectric material is deposited across the oxide liner. A fill oxide is then formed upon the layer of dielectric material. The resulting trench isolation structure includes a low K dielectric material interposed between an oxide liner and a fill oxide. The trench isolation structure is less likely to experience current leakage during the operation of an ensuing integrated circuit employing the isolation structure.
摘要翻译： 提供了一种沟槽隔离结构，其包括具有相对较低的介电常数K的介电材料，K大约小于3.8。 由沟槽隔离结构隔开的与K成正比的有源区之间的电容因此减小。 结果，可以减小隔离结构的横向宽度，而不显着增加这些有源区域之间的电容。 在一个实施例中，用于沟槽隔离结构的制造工艺可以包括在形成有掩模层的半导体衬底内蚀刻沟槽。 在沟槽的侧壁和基底上热生长氧化物衬垫。 一层低K电介质材料沉积在氧化物衬垫两侧。 然后在电介质材料层上形成填充氧化物。 所形成的沟槽隔离结构包括介于氧化物衬垫和填充氧化物之间的低K电介质材料。 在采用隔离结构的随后的集成电路的操作期间，沟槽隔离结构不太可能经历电流泄漏。
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8.发明授权CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions 有权CMOS集成电路具有用于产生与PMOS源极/漏极结不相似的分级NMOS源极/漏极结的牺牲金属间隔物
公开(公告)号：US6107130A
公开(公告)日：2000-08-22
申请号：US189235
申请日：1998-11-10
IPC分类号： H01L21/8238 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/823814 , Y10S257/90
摘要： An integrated circuit is formed whereby junction of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, an MDD area and a heavy concentration source/drain area. Conversely, the PMOS transistor include an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provide lower source/drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.
摘要翻译： 形成集成电路，其中NMOS晶体管的结形成为不同于PMOS晶体管的结。 NMOS晶体管包括LDD区域，MDD区域和重的浓度源极/漏极区域。 相反，PMOS晶体管包括LDD区域和源极/漏极区域。 NMOS晶体管结形成为不同于PMOS晶体管结，以考虑到相掺杂剂相对于PMOS掺杂剂的移动性较小。 因此，LDD面积的减小和包含MDD面积在NMOS器件中提供更低的源极/漏极电阻和更高的欧姆连接性。 PMOS结包括相对较大的LDD面积，以便将高度移动的，高浓度的硼原子从PMOS沟道拉出。
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9.发明授权
公开(公告)号：US6060345A
公开(公告)日：2000-05-09
申请号：US844924
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814
摘要： A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.
摘要翻译： 公开了一种制造具有减小的掩蔽步骤的NMOS和PMOS器件的方法。 该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一和第二有源区上形成栅极材料，在栅极材料上形成第一掩模层， 栅极材料，使用第一掩模层作为蚀刻掩模，以在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，使用第一掩模层将第二导电类型的掺杂剂注入到第一和第二有源区中 作为注入掩模，形成覆盖第一有源区并且包括在第二有源区上方的开口的第二掩模层，以及使用第一和第二掩模层作为注入掩模将第一导电类型的掺杂剂注入到第二有源区中 。 有利地，第一导电类型的掺杂剂在第二有源区域中抵消第二导电类型的掺杂剂，从而在第一有源区域中提供第二导电类型的源极和漏极区域，并且在第二有源区域中提供第一导电类型的源极和漏极区域 具有单个掩蔽步骤，并且不对任一个栅极施加第一和第二导电类型的掺杂剂。
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10.发明授权Transistor with low resistance metal source and drain vertically displaced from the channel 有权具有低电阻金属源和漏极的晶体管垂直从通道移位
公开(公告)号：US6057583A
公开(公告)日：2000-05-02
申请号：US227511
申请日：1999-01-06
IPC分类号： H01L21/266 , H01L21/336 , H01L21/768 , H01L21/8238 , H01L29/417 , H01L29/49 , H01L29/76
CPC分类号： H01L29/66575 , H01L21/266 , H01L21/76895 , H01L21/823814 , H01L29/41775 , H01L29/41783 , H01L29/4966 , H01L29/66537 , H01L29/66545 , Y10S257/902
摘要： A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The source and drain regions of the transistor are configured upon a semiconductor substrate, and the transistor channel is within the substrate. A protective dielectric layer is deposited over the semiconductor substrate. Source/drain trenches are formed in the protective dielectric layer and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which are preferably formed from a low-resistance metal. The resulting transistor may exhibit low contact and series resistances, and increased operating speed.
摘要翻译： 在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻源极和漏极区域提供并形成晶体管。 晶体管的栅极也可以由诸如金属的低电阻材料形成。 晶体管的源极和漏极区域配置在半导体衬底上，并且晶体管沟道在衬底内。 保护介电层沉积在半导体衬底上。 源极/漏极沟槽形成在保护电介质层中，随后填充有牺牲电介质。 位于这些牺牲电介质之间的保护电介质被去除，并被替代为可由低电阻金属形成的侧壁间隔物，栅极电介质和栅极导体。 随后去除牺牲电介质并用优选由低电阻金属形成的源极/漏极区域代替。 所得到的晶体管可以表现出低接触和串联电阻，并且提高了操作速度。
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