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公开(公告)号：US11200927B2
公开(公告)日：2021-12-14
申请号：US16843628
申请日：2020-04-08
Applicant: Micron Technology, Inc.
Inventor： Zhi Qi Huang , Wei Lu Chu , Dong Pan
Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.
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公开(公告)号：US20210327488A1
公开(公告)日：2021-10-21
申请号：US16852019
申请日：2020-04-17
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
IPC: G11C11/22 , G11C11/4074 , G05F1/575 , G05F1/59
Abstract: Methods, systems, and devices for techniques for adjusting current based on operating parameters are described. An apparatus may include an amplifier, a feedback component, and first and second current generators. The amplifier may include an input for receiving a first voltage and an output for outputting a second voltage. The first current generator may be coupled with the output of the amplifier and generate a first current based at least in part on the second voltage. The feedback component may be coupled with the first current generator to modify the first current based at least in part on an operating temperature associated with a memory device. The first current may be proportional to the operating temperature. The second current generator may be coupled with the first current generator to generate a second current based at least in part on the first current modified by the feedback component.
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公开(公告)号：US10943636B1
公开(公告)日：2021-03-09
申请号：US16546152
申请日：2019-08-20
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C7/00 , G11C11/406 , G11C11/408
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for analog row access tracking. A plurality of unit cells are provided, each of which contains one or more analog circuits used to track accesses to a portion of the wordlines of a memory device. When a wordline in the portion is accessed, the unit cell may update an accumulator voltage, for example by adding charge to a capacitor. A comparator circuit may determine when one or more accumulator voltages cross a threshold (e.g., a reference voltage). Responsive to the accumulator voltage crossing the threshold, an aggressor address may be loaded in a targeted refresh queue, or if the aggressor address is already in the queue, a priority flag associated with that address may be set. Aggressor addresses may be provided to have their victims refreshed in an order based on the number of set priority flags.
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公开(公告)号：US10885998B1
公开(公告)日：2021-01-05
申请号：US16681413
申请日：2019-11-12
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
Abstract: A circuit may include a voltage line and latch circuitry. The latch circuitry may be characterized by a switching voltage threshold and may be coupled to the voltage line. The latch circuitry may generate an output used to determine a state of a fuse. The circuit may also include generation circuitry coupled to the latch circuitry via the voltage line, wherein the generation circuitry is configured to pre-charge the voltage line to a first voltage between a system logical low voltage and the switching voltage threshold.
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公开(公告)号：US10833630B2
公开(公告)日：2020-11-10
申请号：US16225678
申请日：2018-12-19
Applicant: MICRON TECHNOLOGY, INC.
IPC: H03B5/04 , G11C7/10 , G11C11/406 , H03K3/03 , H03K4/502 , H03K3/0231 , H03K3/011 , H03B5/24 , H03L1/02
Abstract: Apparatuses and methods for temperature independent oscillator circuits are disclosed herein. An example apparatus may include a pulse generator circuit configured to provide a periodic pulse based on the charging and discharging and discharging of a capacitor and further based on a reference voltage. The pulse generator circuit may include a capacitor coupled between a first reference voltage and a first node, wherein the capacitor is configured to be charged and discharged through the node in response to the periodic pulse, a resistor and a diode coupled in series between a second node and a second reference voltage, and a comparator coupled to the first and second nodes and configured to provide the periodic pulse based on voltages on the first and second nodes, wherein a period of the periodic pulse is based at least on the resistor and the a current.
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Patent Agency Ranking
116.发明申请公开(公告)号：US20200327913A1
公开(公告)日：2020-10-15
申请号：US16823079
申请日：2020-03-18
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
IPC: G11C5/14 , G11C11/4074
Abstract: Systems and devices are provided for fully discharging leakage current generated during standby and/or power down modes regardless of variations in PVT conditions. An apparatus may include a power generation unit that powers components of the apparatus and a bleeder circuit. The bleeder circuit may include an operational amplifier. Further, the bleeder circuit may include leakage current generator circuitry that is coupled to the operational amplifier and generates a first current that mimics leakage current generated by the power generation unit. Furthermore, the bleeder circuit may include leakage current mirroring circuitry that is coupled to an output of the operational amplifier and that generates a second current that mirrors the first current. In addition, the bleeder circuit may also include leakage current bleeder circuitry that is coupled to the leakage current mirroring circuitry and that generates a third current that sinks the leakage current to ground.
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公开(公告)号：US10446195B2
公开(公告)日：2019-10-15
申请号：US15312010
申请日：2016-06-29
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/00 , H03F1/30 , G11C11/16 , G05F3/02 , G05F3/16 , G11C17/18 , G01R19/00 , H03K3/012 , G11C5/14 , G11C29/02 , G05F1/575 , G05F1/595
Abstract: Disclosed are apparatuses and methods for controlling gate-induced drain leakage current in a transistor device. An apparatus may include a first biasing circuit stage configured to provide a biasing voltage on a biasing signal line, the biasing voltage based on a current through a first resistor associated with the first biasing circuit stage, a voltage generation circuit stage coupled to the first biasing circuit stage, the voltage generation circuit stage having an output transistor that is coupled to the biasing signal line through a gate terminal of the output transistor, and an output line coupled to the voltage generation circuit stage and configured to provide an output voltage signal having a steady-state voltage that is less than a power supply voltage by an amount that corresponds to a voltage drop across the first resistor associated with the first biasing circuit stage.
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公开(公告)号：US10373670B1
公开(公告)日：2019-08-06
申请号：US15923235
申请日：2018-03-16
Applicant: Micron Technology, Inc.
Inventor： Zhi Qi Huang , Wei Lu Chu , Hiromasa Noda , Dong Pan
IPC: G11C5/14 , G11C11/4076 , G11C11/4072 , G11C11/4074
Abstract: A memory device includes a memory array including a plurality of memory cells; and an array timer coupled to the memory array, configured to generate an output timing signal based on a V-I stable input and an analog reference signal, wherein: the V-I stable input is from a bandgap supply circuit, the analog reference signal is from an analog reference block, and the output timing signal is configured to control the memory array.
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119.发明授权公开(公告)号：US10250139B2
公开(公告)日：2019-04-02
申请号：US15087271
申请日：2016-03-31
Applicant: Micron Technology, Inc.
Inventor： Yuanzhong Wan , Dong Pan
Abstract: According to one embodiment of this disclosure, an apparatus is disclosed. The apparatus includes a voltage regulator configured to produce a regulated voltage, a plurality of current circuits coupled in parallel between an output node and a power node, each of the plurality of current circuits including first and second transistors coupled in series, the first transistor of each of the plurality of current circuits being biased with the regulated voltage, and a control circuit configured to activate the second transistor of selected one or ones of the plurality of current circuits responsive, at least in part, to a voltage at the output node.
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公开(公告)号：US20190094900A1
公开(公告)日：2019-03-28
申请号：US16203215
申请日：2018-11-28
Applicant: Micron Technology, Inc.
IPC: G05F3/26
Abstract: A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. The reference voltages may be provided from output terminals coupled to the resistors. A reference voltage generator may include a voltage divider, two multiplexers coupled to the voltage divider, an operational amplifier coupled to each multiplexer, and a plurality of resistors coupled between the outputs of the two operational amplifiers. Reference voltages may be provided from output terminals coupled to the resistors.
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