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    Integrated Assemblies, and Methods of Forming Integrated Assemblies
    113.
    发明申请
    Integrated Assemblies, and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20220399440A1

    公开(公告)日：2022-12-15

    申请号：US17890565

    申请日：2022-08-18

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John D. Hopkins

    IPC: H01L29/08 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556

    Abstract: Some embodiments include an integrated assembly having a source structure. The source structure includes, in ascending order, a first conductively-doped semiconductor material, one or more first insulative layers, a second conductively-doped semiconductor material, one or more second insulative layers, and a third conductively-doped semiconductor material. The source structure includes blocks extending through the second conductively-doped semiconductor material. Conductive levels are over the source structure. Channel material extends vertically along the conductive levels, and extends into the source structure to be in direct contact with the second conductively-doped semiconductor material. One or more memory cell materials are between the channel material and the conductive levels. Some embodiments include methods of forming integrated assemblies.

    Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Methods Including A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
    114.
    发明申请
    Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Methods Including A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20220399357A1

    公开(公告)日：2022-12-15

    申请号：US17348021

    申请日：2021-06-15

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

    IPC: H01L27/11556 ,  G11C5/06 ,  G11C5/02 ,  H01L27/11582 ,  H01L23/538 ,  H01L21/768

    Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an tipper portion and a lower portion. The upper portion comprises vertically alternating first tiers and second insulating tiers that are of different composition relative one another. The lower portion comprises an upper polysilicon-comprising layer, a lower polysilicon-comprising layer, an intervening-material layer vertically between the tipper and lower polysilicon-comprising layers. An upper intermediate layer is vertically between the upper polysilicon-comprising layer and the intervening-material layer. A lower intermediate layer is vertically between the lower polysilicon-comprising layer and the intervening-material layer. The lower intermediate layer and the upper intermediate layer comprise at least one of (a), (b), and (c), where (a): a hafnium oxide; (b): a bilayer comprising silicon nitride and comprising silicon dioxide positioned vertically relative one another, the silicon nitride in the bilayer being closer to the intervening-material layer than is the silicon dioxide in the bilayer; and (c): SiOxNy, where each of “x” and “y” is from 1 atomic percent to 90 atomic percent of the total of the Si, the O, and the N in the SiOxNy. Methods are disclosed.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    116.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20220328519A1

    公开(公告)日：2022-10-13

    申请号：US17850214

    申请日：2022-06-27

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John D. Hopkins

    IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/3215 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed and individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor material between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material that is laterally-between the horizontally-elongated lines. After the horizontally-elongated lines are formed, conductive material of a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier, Other embodiments, including structure independent of method, are disclosed.

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