公开(公告)号：US20060044719A1

公开(公告)日：2006-03-02

申请号：US11205378

申请日：2005-08-17

申请人： Zi-Ping Chen ,  Ming-Dou Ker

发明人： Zi-Ping Chen ,  Ming-Dou Ker

IPC分类号： H02H9/00

CPC分类号： H01L27/0255 ,  H01L29/7436

摘要： Diode strings and electrostatic discharge circuits characterized by low current leakage. Each diode region provides a diode and has first and second regions. The first region is of a first conductive type and formed on a substrate, acting as a first electrode of a diode. The second region is of a second conductive type opposite to the first conductive type, formed in the first region and acting as a second electrode of a corresponding diode. The diodes are forward connected in series to form major anode and cathode of the diode string. An isolation region is of the second conductive type to isolate those diode regions. A bias resistor is connected between the isolation region and a first power line. During normal operation, the voltage of the first power line is not within the range between the voltages of the major anode and cathode.

公开(公告)号：US20060027873A1

公开(公告)日：2006-02-09

申请号：US11240475

申请日：2005-10-03

申请人： Ming-Dou Ker ,  Hsin-Chyh Hsu ,  Wen-Yu Lo

发明人： Ming-Dou Ker ,  Hsin-Chyh Hsu ,  Wen-Yu Lo

IPC分类号： H01L23/62

CPC分类号： H01L21/823814 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.

公开(公告)号：US20050270710A1

公开(公告)日：2005-12-08

申请号：US10857836

申请日：2004-06-02

申请人： Ming-Dou Ker ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Kun-Hsien Lin

IPC分类号： H01L27/02 ,  H01L29/74 ,  H02H9/00

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： The present invention relates to an SCR (Silicon Controlled Rectifier) for the ESD (electrostatic discharge) protection comprising two terminal electrodes of a first electrode and a second electrode, a PMOS, an NMOS and an SCR structure. By utilizing an embedded SCR, a whole-chip ESD protection circuit design can be obtained. The present invention is suitable for IC products, and for applications by IC design industries and IC foundry industries.

摘要翻译： 本发明涉及一种用于ESD（静电放电）保护的SCR（硅控整流器），其包括第一电极和第二电极，PMOS，NMOS和SCR结构的两个端电极。 通过利用嵌入式SCR，可以获得全芯片ESD保护电路设计。 本发明适用于IC产品，适用于IC设计行业和IC铸造行业。

公开(公告)号：US20050133869A1

公开(公告)日：2005-06-23

申请号：US10709307

申请日：2004-04-28

申请人： Ming-Dou Ker ,  Kuo-Chun Hsu

发明人： Ming-Dou Ker ,  Kuo-Chun Hsu

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L21/332

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： A double-triggered silicon controller rectifier (SCR) comprises a plurality of N+ diffusion areas, a plurality of P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.

摘要翻译： 双触发硅控制器整流器（SCR）包括多个N +扩散区域，多个P +扩散区域，第一N阱区域，第二N阱区域和形成在P- 基质。 通过浅沟槽隔离（STI）结构隔离N +扩散区域和P +扩散区域。 N +扩散区域中的两个是N型触发端子。 P +扩散区域中的两个是P型触发端子。

公开(公告)号：US20050104641A1

公开(公告)日：2005-05-19

申请号：US10790842

申请日：2004-03-03

申请人： Shih-Lun Chen ,  Ming-Dou Ker

发明人： Shih-Lun Chen ,  Ming-Dou Ker

IPC分类号： H03K3/3565 ,  H03K3/037

CPC分类号： H03K3/3565

摘要： The present invention relates to a Schmitt trigger circuit. The proposed Schmitt trigger circuit can receive the high-voltage input signal but it is consisted by only using the low-voltage devices with thin gate oxide. For example, it is implemented in a 0.13 μm 1V/2.5V Complementary Metal-Oxide Semiconductor (CMOS) process. However, it can be operated in the 3.3 V interface environment without causing the high-voltage-induced gate-oxide reliability problem. It is suitable for the I/O interface circuit to receive the high-voltage input signal and to reject the noise.

摘要翻译： 本发明涉及施密特触发电路。 所提出的施密特触发电路可以接收高电压输入信号，但由仅使用具有薄栅极氧化物的低电压器件组成。 例如，它在0.13毫姆1V / 2.5V互补金属氧化物半导体（CMOS）工艺中实现。 然而，它可以在3.3 V接口环境中工作，而不会引起高压引起的栅极氧化可靠性问题。 它适合于I / O接口电路接收高压输入信号并拒绝噪声。

公开(公告)号：US20050098795A1

公开(公告)日：2005-05-12

申请号：US10956063

申请日：2004-10-04

申请人： Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

发明人： Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L31/062

CPC分类号： H01L27/0262

摘要： A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing ESD protection.

摘要翻译： 高压设备。 在ESD保护器件中将高电压MOS晶体管施加到其中添加掺杂区域的结构，产生具有更短放电路径的寄生半导体可控整流器（SCR），使得SCR具有更快的响应增强ESD保护。

公开(公告)号：US06885534B2

公开(公告)日：2005-04-26

申请号：US10277640

申请日：2002-10-21

申请人： Ming-Dou Ker ,  Cheng-Ming Lee ,  Wen-Yu Lo

发明人： Ming-Dou Ker ,  Cheng-Ming Lee ,  Wen-Yu Lo

IPC分类号： H01L27/02 ,  H02H9/04 ,  H02H1/00

CPC分类号： H01L27/0251 ,  H02H9/046

摘要： The present invention relates to a device for protecting high frequency RF integrated circuits from ESD damage. The device comprises at least one varactor-LC circuit tank stacked to avoid the power gain loss by the parasitic capacitance of ESD circuit. The varactor-LC tank could be designed to resonate at the RF operating frequency to avoid the power gain loss from the parasitic capacitance of ESD circuit. Multiple LC-tanks could be stacked for further reduction in the power gain loss. A reverse-biased diode is used as the varactor for both purposes of impedance matching and effective ESD current discharging. Because the inductor is made of metal, both the inductor and the varactor can discharge ESD current when ESD condition happens. It has a high enough ESD level to prevent ESD discharge.

摘要翻译： 本发明涉及用于保护高频RF集成电路免受ESD损坏的装置。 该装置包括至少一个堆叠的变容二极管LC电路箱，以避免由ESD电路的寄生电容引起的功率增益损失。 变容二极管LC罐可以设计为以RF工作频率谐振，以避免ESD电路的寄生电容产生的功率增益损耗。 可以堆叠多个液相色谱柱，以进一步降低功率增益损失。 反向偏置二极管用作变容二极管，用于阻抗匹配和有效的ESD电流放电。 由于电感由金属制成，所以当ESD条件发生时，电感和变容二极管均可放电ESD电流。 它具有足够高的ESD电平以防止ESD放电。

公开(公告)号：US06867957B1

公开(公告)日：2005-03-15

申请号：US10065364

申请日：2002-10-09

申请人： Paul C. F. Tong ,  Ming-Dou Ker ,  Ping Ping Xu

发明人： Paul C. F. Tong ,  Ming-Dou Ker ,  Ping Ping Xu

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0262 ,  H01L27/0266

摘要： Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.

摘要翻译： 具有非常薄的栅极氧化物的晶体管通过在输出焊盘和接地之间串联两个或更多个晶体管来保护免受氧化物故障。 两个级联晶体管之间的中间源极/漏极节点通常在ESD测试期间浮置，延迟了寄生侧面NPN晶体管的快速恢复导通。 该中间节点用于驱动上触发晶体管的栅极。 下触发晶体管具有通过耦合电容器通过焊盘上的ESD脉冲对其进行充电的栅极节点。 当耦合的ESD脉冲接通触发晶体管时，触发晶体管导通与触发晶体管集成的可控硅整流器（SCR）。

公开(公告)号：US20050012155A1

公开(公告)日：2005-01-20

申请号：US10727550

申请日：2003-12-05

申请人： Ming-Dou Ker ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H01L29/70

CPC分类号： H01L27/0266

摘要： A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

摘要翻译： 一种适用于静电放电（ESD）保护电路的半导体器件，包括半导体衬底，在衬底中形成的第一阱，在衬底中形成的第二阱以及形成在第二阱中的第一掺杂区，其中， 第一阱，第二阱和第一掺杂区域共同形成寄生双极结型晶体管（BJT），其中第一阱是BJT的集电极，第二阱是BJT的基极，第一掺杂区域 是BJT的发射器。

公开(公告)号：US06765771B2

公开(公告)日：2004-07-20

申请号：US09887980

申请日：2001-06-22

申请人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

IPC分类号： H02H900

CPC分类号： H01L27/0262 ,  H01L29/7436 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection component with a deep-N-well structure in CMOS technology and the relevant circuit designs are proposed in this invention. The ESD protection component comprises a lateral silicon controlled rectifier (SCR) and a deep N-well. The SCR comprises a P-type layer, an N-type layer, a first N-well and a first P-well. The P-type layer is used as an anode of the SCR; the N-type layer is used as a cathode of the SCR; the first N-well is located between the P-type layer and the N-type layer and is contacted with the P-type layer; and the first P-well is contacted to the first N-well and the N-type layer. The deep N-well is located between the first P-well and the P-substrate, and is used to isolate the electric connection between the P-substrate and the first P-well. A plurality of these ESD protection components arbitrarily connected in series increases the total holding voltage of ESD protection circuit, thus preventing occurrences of latch-up.

摘要翻译： 本发明提出CMOS技术中具有深N阱结构的ESD保护元件及相关电路设计。 ESD保护组件包括侧向可控硅整流器（SCR）和深N阱。 SCR包括P型层，N型层，第一N阱和第一P阱。 P型层用作SCR的阳极; N型层用作SCR的阴极; 第一N阱位于P型层和N型层之间，并与P型层接触; 并且第一P阱与第一N阱和N型层接触。 深N阱位于第一P阱和P衬底之间，用于隔离P衬底和第一P阱之间的电连接。 串联任意连接的多个ESD保护元件增加了ESD保护电路的总保持电压，从而防止闩锁的发生。