公开(公告)号：US20100239059A1

公开(公告)日：2010-09-23

申请号：US12790274

申请日：2010-05-28

申请人： Hirokazu Sugimoto ,  Toru Iwata

发明人： Hirokazu Sugimoto ,  Toru Iwata

IPC分类号： H04L7/00

CPC分类号： H04L7/0008 ,  H03L7/06 ,  H04L7/0091 ,  H04L7/0337

摘要： A data transmission circuit transmits transmission data to a receiving apparatus. The clock transmission circuit transmits a transmission clock to the receiving apparatus when the transmission data is transmitted by the data transmission circuit. The phase control circuit varies a phase of the transmission clock to a phase different from that of the transmission data after the transmission clock is transmitted from the clock transmission circuit.

摘要翻译： 数据发送电路将发送数据发送到接收装置。 当数据传输电路发送传输数据时，时钟传输电路将传输时钟传送到接收设备。 在从时钟发送电路发送发送时钟之后，相位控制电路将发送时钟的相位改变为与发送数据的相位不同的相位。

公开(公告)号：US07675314B2

公开(公告)日：2010-03-09

申请号：US12081154

申请日：2008-04-11

申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

IPC分类号： H03K19/007

CPC分类号： H04L25/493

摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

摘要翻译： 在通过电缆接收数据和时钟信号的接收机电路中，通过频率检测电路检测基于数据或时钟信号获得的信号的转变次数，并且当转换次数不大于预定的集合 输出用于复位包括在数据处理单元中的串行 - 并行转换器电路的操作的信号，以便控制接收数据的输出。 因此，在不提供上拉电阻器和下拉电阻器的情况下，可以以低功耗检测电缆的断开，并且可以提高抗噪声性能。

公开(公告)号：US20100002822A1

公开(公告)日：2010-01-07

申请号：US12374743

申请日：2006-11-15

申请人： Yukio Arima ,  Akinori Shinmyo ,  Toru Iwata

发明人： Yukio Arima ,  Akinori Shinmyo ,  Toru Iwata

IPC分类号： H04L7/00

CPC分类号： H03L7/089 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0337

摘要： A comparison period detecting unit (11) defines, as a comparison period, a period between a rising edge of a first clock signal and a rising edge of a second clock signal, and detects the presence or absence of transition of a data signal during the comparison period. A phase relationship detecting unit (12) detects a phase relationship between the data signal and a reference clock signal, and outputs a result of detection of the phase relationship when the comparison period detecting unit (11) detects transition of the data signal during the comparison period.

摘要翻译： 比较周期检测单元（11）将第一时钟信号的上升沿和第二时钟信号的上升沿之间的周期定义为比较周期，并且在第一时钟信号的上升沿期间检测数据信号的转换是否存在 比较期 相位关系检测单元（12）检测数据信号和参考时钟信号之间的相位关系，并且当比较周期检测单元（11）在比较期间检测到数据信号的转变时，输出相位关系的检测结果 期。

公开(公告)号：US20090262876A1

公开(公告)日：2009-10-22

申请号：US12090774

申请日：2006-03-10

申请人： Yukio Arima ,  Toru Iwata ,  Makoto Miyake ,  Takefumi Yoshikawa

发明人： Yukio Arima ,  Toru Iwata ,  Makoto Miyake ,  Takefumi Yoshikawa

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/0891

摘要： A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the process of determining whether a data edge lies within the window are performed in parallel to each other, and the phase comparison result is output only if the data edge lies within the window. With this configuration, it is possible to perform an accurate phase comparison process with no errors without requiring high-precision delay circuits.

摘要翻译： 用于高速数据通信的定时恢复过程中的相位比较处理定义数据窗口并将窗口中的时钟的相位与数据边缘的相位进行比较，以实现并行处理，其中相位比较和 执行数据边缘位于窗口内的处理是彼此并行执行的，并且仅当数据边缘位于窗口内时才输出相位比较结果。 利用这种配置，可以在不需要高精度延迟电路的情况下，无误地执行精确的相位比较处理。

公开(公告)号：US20080303567A1

公开(公告)日：2008-12-11

申请号：US12033707

申请日：2008-02-19

申请人： Shiro SAKIYAMA ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

发明人： Shiro SAKIYAMA ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/0895

摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

摘要翻译： 延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。 信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。 电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉） （或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

公开(公告)号：US20080247492A1

公开(公告)日：2008-10-09

申请号：US11597794

申请日：2005-02-01

申请人： Hirokazu Sugimoto ,  Toru Iwata

发明人： Hirokazu Sugimoto ,  Toru Iwata

IPC分类号： H04L27/06

CPC分类号： G11B20/10009 ,  G09G5/006 ,  G09G5/12 ,  G11B20/10222 ,  G11B20/10425 ,  G11B20/14 ,  G11B2020/10592 ,  G11B2220/2562 ,  H04N5/775 ,  H04N5/781

摘要： In a signal receiving circuit including a plurality of input channels, there are provided N input detection circuits 2a to 2n for receiving clock signals S1-c to SN-c included in N channels of signals S1 to SN. Each of the input detection circuits 2a to 2n detects the transition of the input signal of the corresponding channel and further confirms that the signal of the corresponding channel is being received after the transition detection to thereby detect the input of the signal of the corresponding channel. If one of the input detection circuits 2a to 2n detects the input of the signal of the corresponding channel, the selection circuit 3 selects and outputs the clock signal and the data signal in the signal of the channel of which the input is detected. The selected output signal is successively subjected to input processes through one each of the phase synchronization circuit 4, the serial/parallel conversion circuit 5, etc., which are shared by N channels. Therefore, there is needed only one each of input processing circuits such as the serial/parallel conversion circuit, thus saving the stand-by current for these input processing circuits.

摘要翻译： 在包括多个输入通道的信号接收电路中，设置有N个输入检测电路2a至2n，用于接收N个信号S 1至SN中包含的时钟信号S 1 -c至SN-c。 每个输入检测电路2a至2n检测相应信道的输入信号的转换，并进一步确认在转换检测之后正在接收相应信道的信号，从而检测相应信道的信号的输入 渠道。 如果输入检测电路2a至2n中的一个检测到对应信道的信号的输入，则选择电路3选择并输出检测到输入的信道的信号中的时钟信号和数据信号。 所选择的输出信号通过由N个信道共享的相位同步电路4，串行/并行转换电路5等中的每一个依次进行输入处理。 因此，仅需要一个输入处理电路，例如串行/并行转换电路，从而节省了用于这些输入处理电路的备用电流。

公开(公告)号：US07397268B2

公开(公告)日：2008-07-08

申请号：US11653340

申请日：2007-01-16

申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

IPC分类号： H03K19/007

CPC分类号： H04L25/493

摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

公开(公告)号：US20070115025A1

公开(公告)日：2007-05-24

申请号：US11653340

申请日：2007-01-16

申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

IPC分类号： H03K19/007

CPC分类号： H04L25/493

摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

公开(公告)号：US20070041483A1

公开(公告)日：2007-02-22

申请号：US11586587

申请日：2006-10-26

申请人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

发明人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

IPC分类号： H03D3/24

CPC分类号： H04L25/45 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0891 ,  H04L7/033

摘要： A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

摘要翻译： 驱动器和接收器提供数据信号，其基于具有常规位模式的串行数据，例如时钟，其包括在调整周期期间彼此交替的1和0，并且基于具有任意的串行数据 在调整周期后的转移期间的位模式。 占空因数控制器调节驱动器或接收器的数据转换特性，使得从接收器提供的数据信号的占空比在调整周期中等于50％，并且具有被调整的数据转换特性。 时钟恢复单元恢复与在传送时段中从接收器提供的数据信号同步的时钟，并且基于来自数据信号的经调整的转换特性。

公开(公告)号：US07136441B2

公开(公告)日：2006-11-14

申请号：US10038613

申请日：2002-01-08

申请人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

发明人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

IPC分类号： H04L7/00

CPC分类号： H04L25/45 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0891 ,  H04L7/033

摘要： A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.