公开(公告)号：US20080224261A1

公开(公告)日：2008-09-18

申请号：US12127080

申请日：2008-05-27

申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

IPC分类号： H01L23/525 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor stricture Methods of making and programming the fuse/anti-fuse structures are also provided.

摘要翻译： 提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构， 其中空腔限定结构的至少一部分由内部导体结构，绝缘层和外部导体狭窄中的至少一个形成。还提供了制造和编程熔丝/反熔丝结构的方法。

公开(公告)号：US07420836B1

公开(公告)日：2008-09-02

申请号：US11674292

申请日：2007-02-13

申请人： Keunwoo Kim ,  Rajiv V. Joshi ,  Vinod Ramadurai

发明人： Keunwoo Kim ,  Rajiv V. Joshi ,  Vinod Ramadurai

IPC分类号： G11C11/40

CPC分类号： G11C11/412 ,  G11C11/413

摘要： A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.

摘要翻译： 用于与READ和WRITE字线以及READ和WRITE位线互连的存储单元包括逻辑存储元件，例如由第一反相器形成的触发器和与第一反相器交叉耦合的第二反相器。 存储元件具有第一和第二端子以及被配置为与第一电源电压互连的存储元件电源电压端子。 WRITE访问设备被配置为在WRITE字线的控制下选择性地将第一终端与WRITE位线互连，并且一对串行READ访问设备被配置为当READ字线活动时将READ位线接地，并且 第二终端处于高逻辑级。 当将大于第一电源电压的第二电源电压施加到写字线时，基本上不使用互补的写位线，可以将逻辑“1”写入存储元件。

公开(公告)号：US20080181029A1

公开(公告)日：2008-07-31

申请号：US11668545

申请日：2007-01-30

申请人： Rajiv V. Joshi ,  Jae-Joon Kim ,  Rahul M. Rao

发明人： Rajiv V. Joshi ,  Jae-Joon Kim ,  Rahul M. Rao

IPC分类号： G11C7/00 ,  G11C11/416

CPC分类号： G11C7/22 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/18 ,  G11C11/412 ,  G11C11/413

摘要： In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line (WBL) are decoupled, RBL and WBL can be accessed simultaneously. Hence, the WRITE in the n-th cycle can be delayed to the n+1-th cycle as far as there is no data hazard such as reading data from memory before correct data are actually written to memory. As a result, there is no bandwidth loss, although the latency of the WRITE operation increases. WRITE stability issues in previous configurations with decoupled RBL and WBL are thus addressed.

摘要翻译： 在存储器电路中，读取沿着所选字线的所有单元的数据。 然后，将读取的数据写回到半选择的单元，并且在下一个周期中将新数据写入所选择的单元。 在读取位线（RBL）和写入位线（WBL）解耦的情况下，可以同时访问RBL和WBL。 因此，第n个周期中的写入可以延迟到第n + 1个周期，只要没有数据危险，例如在正确数据实际写入存储器之前从存储器读取数据。 因此，尽管WRITE操作的延迟增加，但是没有带宽损失。 因此，解决了具有去耦RBL和WBL的以前配置中的写稳定性问题。

公开(公告)号：US07403412B2

公开(公告)日：2008-07-22

申请号：US11782282

申请日：2007-07-24

申请人： Yuen H. Chan ,  Rajiv V. Joshi ,  Donald W. Plass

发明人： Yuen H. Chan ,  Rajiv V. Joshi ,  Donald W. Plass

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C11/412 ,  G11C11/417

摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

摘要翻译： 可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。 阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。 正常基极FET具有基极阈值，并且定制的FET具有高于阈值。 在多电源芯片中，具有定制FET的电路由增加的电源电压供电。

公开(公告)号：US07390730B2

公开(公告)日：2008-06-24

申请号：US11742147

申请日：2007-04-30

申请人： Jack A. Mandelman ,  Louis C. Hsu ,  Rajiv V. Joshi

发明人： Jack A. Mandelman ,  Louis C. Hsu ,  Rajiv V. Joshi

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1203 ,  H01L29/94

摘要： A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

摘要翻译： 提供一种具有体电容板的半导体结构，其形成有确保体电容板与源极线（SL）扩散和位线扩散两者自对准的工艺。 因此，SL和位线扩散和体电容板之间的重叠量被精确地控制。 更具体地说，本发明通过使用确保存在1）板和源极/漏极扩散之间的最小重叠的过程形成具有侧壁电容器板的1T无电容的SOI体电荷存储单元的结构，以及2）最小重叠 在本发明中获得的精确控制并且不受对准公差的影响。 与现有技术相比，本发明的电池产生更大的信号余量，改善的性能，更小的芯片尺寸和降低的动态功耗。

公开(公告)号：US07274590B2

公开(公告)日：2007-09-25

申请号：US11483117

申请日：2006-07-06

申请人： Rajiv V. Joshi

发明人： Rajiv V. Joshi

IPC分类号： G11C11/00

CPC分类号： G11C11/413 ,  G11C8/08

摘要： A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or gate the wordline signal until an enable signal has arrived at the logic circuit. The access device improves stability and eliminates early read problems.

摘要翻译： 随机存取存储器包括具有存取装置的存储单元。 接入设备根据字线上的信号被接通或断开，以通过接入设备进行存储器操作。 逻辑电路耦合到字线以延迟或栅极字线信号，直到使能信号到达逻辑电路。 访问设备提高了稳定性并消除了早期读取问题。

公开(公告)号：US07266707B2

公开(公告)日：2007-09-04

申请号：US10942419

申请日：2004-09-16

申请人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka ,  Rajiv V. Joshi

发明人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka ,  Rajiv V. Joshi

IPC分类号： G06F1/00

CPC分类号： G06F1/3228

摘要： A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two power-gated modes. Normally the power rail in the power-gated second pipeline stage is charged to a first voltage potential of a pipeline power supply. In the first power gated mode, the power rail is charged to a threshold voltage below the first voltage potential to reduce leakage. In the second power gated mode, the power rail is decoupled from the first voltage potential. A power-gated third pipeline stage has its power rail either coupled to the first voltage potential or power-gated where its power rail is decoupled from the first voltage potential. The power rail of the second power-gated pipeline stage charges to the first voltage potential before the third power-gated pipeline stage.

摘要翻译： 低功耗流水线电路架构具有电源分配管线级。 第一个流水线阶段是非功率门控，用于在接收到有效的数据信号后处理输入数据的快速响应。 电源门控第二管道级具有两个电源门控模式。 通常，电源门控第二管线级中的电源轨被充电到管线电源的第一电压电位。 在第一电源门控模式中，电力轨被充电到低于第一电压电位的阈值电压以减少泄漏。 在第二电源门控模式下，电源轨与第一电压电位分离。 电源门控第三管线级具有其电源轨或者耦合到第一电压电势或电源门控，其电源轨与第一电压电势分离。 第二电力门控管道阶段的电力轨道在第三电力门控管道阶段之前充电到第一电压电位。

公开(公告)号：US07236408B2

公开(公告)日：2007-06-26

申请号：US11184698

申请日：2005-07-19

申请人： Rajiv V. Joshi

发明人： Rajiv V. Joshi

IPC分类号： G11C16/04

CPC分类号： G11C11/413 ,  G11C7/1051 ,  G11C7/1078

摘要： Techniques are provided for selectively biasing wells in a circuit, such as a Complementary Metal Oxide Semiconductor (CMOS) circuit, that has two types of transistors, one type formed on a substrate and another type formed on the wells. For example, the circuit can be a memory circuit, and the selective well bias can be changed depending on whether a READ or WRITE operation is being conducted. In another aspect, cells in a memory circuit can be subjected to variable bias depending on conditions, such as, again, whether a READ or WRITE operation is underway.

公开(公告)号：US07180818B2

公开(公告)日：2007-02-20

申请号：US10996311

申请日：2004-11-22

申请人： Rajiv V. Joshi ,  Azeez Bhavnagarwala

发明人： Rajiv V. Joshi ,  Azeez Bhavnagarwala

IPC分类号： G11C8/00

CPC分类号： G11C11/412 ,  G11C8/16

摘要： A multi-port register file, integrated circuit (IC) chip including one or more multi-port register files and method of reading data from the multi-port register file. The supply to storage latches in multi-port register file is selectively bootstrapped above the supply voltage during accesses.

摘要翻译： 多端口寄存器文件，包括一个或多个多端口寄存器文件的集成电路（IC）芯片以及从多端口寄存器文件读取数据的方法。 在多端口寄存器文件中的存储锁存器的供应在访问期间选择性地被引导到电源电压之上。

公开(公告)号：US07176508B2

公开(公告)日：2007-02-13

申请号：US10899768

申请日：2004-07-27

申请人： Rajiv V. Joshi ,  Sukhvinder S. Kang

发明人： Rajiv V. Joshi ,  Sukhvinder S. Kang

IPC分类号： H01L23/58

CPC分类号： H01L22/34 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a temperature sensor for an integrated circuit having at least one field effect transistor (FET) having a polysilicon gate, in which a current and a voltage is supplied to the polysilicon gate, changes in the current and the voltage of the polysilicon gate are monitored, wherein the polysilicon gate of the at least one FET is electrically isolated from other components of the integrated circuit, and the changes in the current or voltage are used to calculate a change in resistance of the polysilicon gate, and the change in resistance of the polysilicon gate is used to calculate a temperature change within the integrated circuit.

摘要翻译： 公开了一种用于集成电路的温度传感器，其具有至少一个具有多晶硅栅极的场效应晶体管（FET），其中电流和电压被提供给多晶硅栅极，多晶硅栅极的电流和电压的变化是 监控，其中所述至少一个FET的多晶硅栅极与所述集成电路的其它部件电隔离，并且使用所述电流或电压的变化来计算所述多晶硅栅极的电阻变化以及所述多晶硅栅极的电阻变化 多晶硅栅极用于计算集成电路内的温度变化。