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公开(公告)号：US20090242873A1
公开(公告)日：2009-10-01
申请号：US12058101
申请日：2008-03-28
申请人： Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Robert S. Chau
发明人： Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Robert S. Chau
IPC分类号： H01L29/12 , H01L21/338
CPC分类号： H01L29/7783 , H01L29/42316 , H01L29/7784
摘要： Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a back gate layer coupled to the first barrier layer wherein the back gate layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the back gate layer having a first bandgap, a second barrier layer coupled to the back gate layer wherein the second barrier layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the second barrier layer having a second bandgap that is relatively larger than the first bandgap, and a quantum well channel coupled to the second barrier layer, the quantum well channel having a third bandgap that is relatively smaller than the second bandgap.
摘要翻译： 通常描述用于减少短通道效应的半导体异质结构。 在一个示例中，设备包括半导体衬底，耦合到半导体衬底的一个或多个缓冲层，耦合到一个或多个缓冲层的第一势垒层，耦合到第一阻挡层的背栅层，其中背栅层 包括III-V族半导体材料，II-VI族半导体材料或其组合，所述背栅层具有第一带隙，耦合到所述背栅层的第二阻挡层，其中所述第二阻挡层包括III- V族半导体材料，II-VI族半导体材料或其组合，所述第二阻挡层具有相对大于所述第一带隙的第二带隙，以及耦合到所述第二阻挡层的量子阱沟道，所述量子阱沟道具有 相对小于第二带隙的第三带隙。
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公开(公告)号：US08748269B2
公开(公告)日：2014-06-10
申请号：US13969354
申请日：2013-08-16
IPC分类号： H01L21/338
CPC分类号： H01L29/66666 , H01L29/2003 , H01L29/4236 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.
摘要翻译： 描述了基于量子阱的半导体器件和形成量子阱基半导体器件的方法。 一种方法包括提供设置在衬底上方并包括量子阱沟道区的异质结构。 该方法还包括在量子阱沟道区上方形成源极和漏极材料区域。 该方法还包括在源极和漏极材料区域中形成沟槽以提供与漏极区域分离的源极区域。 该方法还包括在沟槽中，在源极和漏极区之间形成栅极电介质层; 以及在所述沟槽中形成栅电极，在所述栅介质层上方。
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公开(公告)号：US20130337623A1
公开(公告)日：2013-12-19
申请号：US13969354
申请日：2013-08-16
IPC分类号： H01L29/66
CPC分类号： H01L29/66666 , H01L29/2003 , H01L29/4236 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.
摘要翻译： 描述了基于量子阱的半导体器件和形成量子阱基半导体器件的方法。 一种方法包括提供设置在衬底上方并包括量子阱沟道区的异质结构。 该方法还包括在量子阱沟道区上方形成源极和漏极材料区域。 该方法还包括在源极和漏极材料区域中形成沟槽以提供与漏极区域分离的源极区域。 该方法还包括在沟槽中，在源极和漏极区之间形成栅极电介质层; 以及在所述沟槽中形成栅电极，在所述栅介质层上方。
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公开(公告)号：US08227833B2
公开(公告)日：2012-07-24
申请号：US12646408
申请日：2009-12-23
IPC分类号： H01L29/66
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/513 , H01L29/66431 , H01L29/66462
摘要： Non-silicon metal-insulator-semiconductor (MIS) devices and methods of forming the same. The non-silicon MIS device includes a gate dielectric stack which comprises at least two layers of non-native oxide or nitride material. The first material layer of the gate dielectric forms an interface with the non-silicon semiconductor surface and has a lower dielectric constant than a second material layer of the gate dielectric. In an embodiment, a dual layer including a first metal silicate layer and a second oxide layer provides both a good quality oxide-semiconductor interface and a high effective gate dielectric constant.
摘要翻译： 非硅金属绝缘体半导体（MIS）器件及其形成方法。 非硅MIS器件包括包含至少两层非自然氧化物或氮化物材料的栅极电介质叠层。 栅极电介质的第一材料层与非硅半导体表面形成界面，并且具有比栅极电介质的第二材料层更低的介电常数。 在一个实施例中，包括第一金属硅酸盐层和第二氧化物层的双层提供良好质量的氧化物半导体界面和高有效栅极介电常数。
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公开(公告)号：US20110147710A1
公开(公告)日：2011-06-23
申请号：US12646408
申请日：2009-12-23
IPC分类号： H01L29/78 , H01L29/12 , H01L21/336
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/513 , H01L29/66431 , H01L29/66462
摘要： Non-silicon metal-insulator-semiconductor (MIS) devices and methods of forming the same. The non-silicon MIS device includes a gate dielectric stack which comprises at least two layers of non-native oxide or nitride material. The first material layer of the gate dielectric forms an interface with the non-silicon semiconductor surface and has a lower dielectric constant than a second material layer of the gate dielectric. In an embodiment, a dual layer including a first metal silicate layer and a second oxide layer provides both a good quality oxide-semiconductor interface and a high effective gate dielectric constant.
摘要翻译： 非硅金属绝缘体半导体（MIS）器件及其形成方法。 非硅MIS器件包括包含至少两层非自然氧化物或氮化物材料的栅极电介质叠层。 栅极电介质的第一材料层与非硅半导体表面形成界面，并且具有比栅极电介质的第二材料层更低的介电常数。 在一个实施例中，包括第一金属硅酸盐层和第二氧化物层的双层提供良好质量的氧化物半导体界面和高有效栅极介电常数。
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116.发明授权Quantum well field-effect transistors with composite spacer structures, apparatus made therewith, and methods of using same 有权具有复合间隔结构的量子井场效应晶体管，由其制成的器件及其使用方法公开(公告)号：US07868318B2
公开(公告)日：2011-01-11
申请号：US12291231
申请日：2008-11-07
IPC分类号： H01L31/00
CPC分类号： H01L29/7783 , H01L29/205 , H01L29/517 , H01L29/7784
摘要： A quantum well (QW) layer is provided in a semiconductive device. The QW layer is covered with a composite spacer above QW layer. The composite spacer includes an InP spacer first layer and an InAlAs spacer second layer above and on the InP spacer first layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.
摘要翻译： 在半导体器件中提供量子阱（QW）层。 QW层覆盖有QW层以上的复合间隔物。 复合间隔物包括在InP间隔物第一层上方和之上的InP间隔物第一层和InAlAs间隔物第二层。 半导体器件包括分别在QW层下方和上方的InGaAs底部和顶部势垒层。 半导体器件还包括位于栅极凹槽中的InP间隔物第一层上的高k栅介质层。 形成QW层的方法包括使用切断的半导体衬底。
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117.发明申请Quantum well field-effect transistors with composite spacer structures, apparatus made therewith, and methods of using same 有权具有复合间隔结构的量子井场效应晶体管，由其制成的器件及其使用方法公开(公告)号：US20100117062A1
公开(公告)日：2010-05-13
申请号：US12291231
申请日：2008-11-07
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L29/7783 , H01L29/205 , H01L29/517 , H01L29/7784
摘要： A quantum well (QW) layer is provided in a semiconductive device. The QW layer is covered with a composite spacer above QW layer. The composite spacer includes an InP spacer first layer and an InAlAs spacer second layer above and on the InP spacer first layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.
摘要翻译： 在半导体器件中提供量子阱（QW）层。 QW层覆盖有QW层以上的复合间隔物。 复合间隔物包括在InP间隔物第一层上方和之上的InP间隔物第一层和InAlAs间隔物第二层。 半导体器件包括分别在QW层下方和上方的InGaAs底部和顶部势垒层。 半导体器件还包括位于栅极凹槽中的InP间隔物第一层上的高k栅介质层。 形成QW层的方法包括使用切断的半导体衬底。
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118.发明授权Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface 有权具有保形金属栅电极和栅极电介质界面的氮掺杂的非平面III-V场效应晶体管公开(公告)号：US08890264B2
公开(公告)日：2014-11-18
申请号：US13627971
申请日：2012-09-26
申请人： Gilbert Dewey , Robert S. Chau , Marko Radosavljevic , Han Wui Then , Scott B. Clendenning , Ravi Pillarisetty
发明人： Gilbert Dewey , Robert S. Chau , Marko Radosavljevic , Han Wui Then , Scott B. Clendenning , Ravi Pillarisetty
CPC分类号： H01L29/66803 , B82Y10/00 , H01L21/2233 , H01L21/228 , H01L21/28264 , H01L29/0665 , H01L29/0673 , H01L29/20 , H01L29/42392 , H01L29/66522 , H01L29/78681 , H01L29/78696
摘要： A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.
摘要翻译： 具有非平面晶体管沟道区域的III-V族半导体表面的高k栅极电介质界面是非定向掺杂氮气的。 在纳米线实施例中，通过将栅极电介质暴露于液体，蒸气，气体，等离子体或固态氮源，在共形栅极电极沉积之前或同时进行高k栅介质界面的非定向氮掺杂 。 在实施例中，栅极电极金属被共形沉积在栅极电介质上，并且执行退火以沿着非平面III-V半导体界面均匀地在栅极电介质内积累氮。
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公开(公告)号：US20120298958A1
公开(公告)日：2012-11-29
申请号：US13571121
申请日：2012-08-09
IPC分类号： H01L29/15 , H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L29/2003 , H01L29/4236 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.
摘要翻译： 描述了基于量子阱的半导体器件和形成量子阱基半导体器件的方法。 一种方法包括提供设置在衬底上方并包括量子阱沟道区的异质结构。 该方法还包括在量子阱沟道区上方形成源极和漏极材料区域。 该方法还包括在源极和漏极材料区域中形成沟槽以提供与漏极区域分离的源极区域。 该方法还包括在沟槽中，在源极和漏极区之间形成栅极电介质层; 以及在所述沟槽中形成栅电极，在所述栅介质层上方。
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公开(公告)号：US20100163945A1
公开(公告)日：2010-07-01
申请号：US12319101
申请日：2008-12-30
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10832 , H01L27/10861 , H01L27/10867 , H01L27/1087 , H01L27/10876 , H01L28/90 , H01L29/66666 , H01L29/7827
摘要： An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.
摘要翻译： 嵌入式存储单元包括半导体衬底（110），具有至少部分地嵌入在半导体衬底中的源极/漏极区域（121）的晶体管（120）以及至少部分地嵌入在半导体衬底中的电容器（130）。 电容器包括通过第一电绝缘材料（133）彼此电绝缘的第一电极（131）和第二电极（132）。 第一电极电连接到半导体衬底，第二电极电连接到晶体管的源极/漏极区域。
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