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    On-chip memory cell and method of manufacturing same
    3.
    发明申请
    On-chip memory cell and method of manufacturing same 审中-公开
    片上存储单元及其制造方法

    公开(公告)号：US20080237678A1

    公开(公告)日：2008-10-02

    申请号：US11729192

    申请日：2007-03-27

    申请人： Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Dinesh Somasekhar ,  Ali Keshavarzi

    发明人： Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Dinesh Somasekhar ,  Ali Keshavarzi

    IPC分类号： H01L27/108 ,  H01L21/336

    CPC分类号： H01L27/10873 ,  H01L27/10826 ,  H01L29/785

    摘要： An on-chip memory cell comprises a tri-gate access transistor (145) and a tri-gate capacitor (155). The on-chip memory cell may be an embedded DRAM on a three-dimensional tri-gate transistor and capacitor structures which is fully compatible with existing tri-gate logic transistor fabrication process. Embodiments of the invention use the high fin aspect ratio and inherently superior surface area of the tri-gate transistors to replace the “trench” capacitor in a commodity DRAM with an inversion mode tri-gate capacitor. The tall sidewalls of the tri-gate transistor provide large enough surface area to provide storage capacitance in a small cell area.

    摘要翻译： 片上存储单元包括三栅极存取晶体管（145）和三栅极电容器（155）。 片上存储器单元可以是三维三栅晶体管上的嵌入式DRAM和与现有三栅逻辑晶体管制造工艺完全兼容的电容器结构。 本发明的实施例使用三栅极晶体管的高翅片长宽比和固有优越的表面积来替代具有反向模式三栅极电容器的商品DRAM中的“沟槽”电容器。 三栅极晶体管的高侧壁提供足够大的表面积，以在小单元区域中提供存储电容。

    Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application
    5.
    发明申请
    Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application 审中-公开
    集成电路，含有1T-1C的嵌入式存储单元以及用于嵌入式存储器应用的1T-1C存储单元的制造方法

    公开(公告)号：US20100155801A1

    公开(公告)日：2010-06-24

    申请号：US12317507

    申请日：2008-12-22

    申请人： Brian S. Doyle ,  Dinesh Somasekhar ,  Gilbert Dewey ,  Satyarth Suri

    发明人： Brian S. Doyle ,  Dinesh Somasekhar ,  Gilbert Dewey ,  Satyarth Suri

    IPC分类号： H01L29/94 ,  H01L29/06 ,  H01L21/8242

    CPC分类号： H01L28/90 ,  H01L27/10894 ,  H01L27/10897

    摘要： An integrated circuit includes a semiconducting substrate (110), electrically conductive layers (120) over the semiconducting substrate, and a capacitor (130) at least partially embedded within the semiconducting substrate such that the capacitor is entirely underneath the electrically conductive layers. A storage node voltage is on an outside layer (132) of the capacitor. In the same or another embodiment, the integrated circuit may act as a 1T-1C embedded memory cell including the semiconducting substrate, an electrically insulating stack (160) over the semiconducting substrate, a transistor (140) including a source/drain region (142) within the semiconducting substrate and a gate region (141) above the semiconducting substrate, a trench (111) extending through the electrically insulating layers and into the semiconducting substrate, a first electrically insulating layer (131) located within the trench, and the capacitor located within the trench interior to the first electrically insulating layer.

    摘要翻译： 集成电路包括半导体衬底（110），半导体衬底上的导电层（120）和至少部分地嵌入在半导体衬底内的电容器（130），使得电容器完全在导电层的下面。 存储节点电压位于电容器的外层（132）上。 在相同或另一个实施例中，集成电路可以用作包括半导体衬底的1T-1C嵌入式存储单元，半导体衬底上的电绝缘堆叠（160），包括源极/漏极区域（142）的晶体管（140） ）和在半导体衬底上方的栅极区（141），延伸穿过电绝缘层并进入半导体衬底的沟槽（111），位于沟槽内的第一电绝缘层（131）和电容器 位于第一电绝缘层的沟槽内部。

    Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method
    8.
    发明授权
    Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method 有权
    三维应变量子阱和三维应变表面通道的Ge约束法

    公开(公告)号：US07767560B2

    公开(公告)日：2010-08-03

    申请号：US11864963

    申请日：2007-09-29

    申请人： Been-Yih Jin ,  Robert S. Chau ,  Brian S. Doyle ,  Jack T. Kavalieros

    发明人： Been-Yih Jin ,  Robert S. Chau ,  Brian S. Doyle ,  Jack T. Kavalieros

    IPC分类号： H01L21/36 ,  H01L21/20

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66818 ,  H01L29/7851

    摘要： The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 本公开描述了通过Ge约束法实现3D（三维）应变高迁移量子阱结构和3D应变表面通道结构的方法和装置。 一个示例性设备可以包括在Si衬底上的第一梯度SiGe鳍。 第一级的SiGe鳍可以具有大于约60％的最大Ge浓度。 Ge量子阱可以在第一等级的SiGe鳍上，SiGe量子阱上阻挡层可以在Ge量子阱上。 示例性设备还可以包括在Si衬底上的第二渐变SiGe鳍。 第二级的SiGe鳍可以具有小于约40％的最大Ge浓度。 Si活性沟道层可以在第二级别的SiGe鳍上。 可以使用诸如III-V族半导体的其它高迁移率材料作为活性通道材料。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin
    9.
    发明授权
    Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin 有权
    通过结合部分金属翅片来减少多栅极器件的外部电阻

    公开(公告)号：US07763943B2

    公开(公告)日：2010-07-27

    申请号：US11964623

    申请日：2007-12-26

    申请人： Ravi Pillarisetty ,  Uday Shah ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

    发明人： Ravi Pillarisetty ,  Uday Shah ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.

    摘要翻译： 通常描述通过结合部分金属翅片来降低多栅极器件的外部电阻。 在一个示例中，设备包括半导体衬底和与半导体衬底耦合的多栅极晶体管器件的一个或多个鳍片，该一个或多个鳍片具有栅极区域，源极区域和漏极区域，栅极区域 设置在源极和漏极区域之间，其中一个或多个鳍片的栅极区域包括半导体材料，并且其中一个或多个鳍片的源极和漏极区域包括金属部分和半导体部分，金属部分和半导体 部分联接在一起。

    Tri-gate patterning using dual layer gate stack
    10.
    发明授权
    Tri-gate patterning using dual layer gate stack 有权
    使用双层栅极堆叠的三栅极图案化

    公开(公告)号：US07745270B2

    公开(公告)日：2010-06-29

    申请号：US12006047

    申请日：2007-12-28

    申请人： Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Been-Yih Jin

    发明人： Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Been-Yih Jin

    IPC分类号： H01L21/84

    CPC分类号： H01L21/823821 ,  H01L29/66795 ,  H01L29/785

    摘要： In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A polysilicon layer is formed over the silicon germanium layer and is polished. The polysilicon layer over the first work function metal layer is thicker than the polysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the polysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.

    摘要翻译： 通常，在一个方面，一种方法包括在半导体衬底中形成n扩散鳍和p扩散鳍。 在衬底上形成高介电常数层。 在n扩散翅片上形成第一功函数金属层，并在n扩散鳍片上形成比第一功函数金属层厚的第二功函数金属层。 在第一和第二功函数金属层上形成硅锗层。 在硅锗层上形成多晶硅层并进行抛光。 第一功函数金属层上的多晶硅层比第二功函数金属层上的多晶硅层厚。 硬掩模被图案化并用于蚀刻多晶硅层和硅锗层以产生栅极堆叠。 硅锗层的蚀刻速率比第一功函数金属层更快。