Abstract:
Systems, internal processors, and methods of parallel data processing in an internal processor are provided. In one embodiment, an external controller sends instructions to a memory device, and the internal processor on the memory device executes the instructions on the data. The internal processor may include one or more arithmetic logic units (ALUs), and each ALU may perform an operation on an entire operand, such that one or more operands may be processed in parallel by one or more ALUs in the internal processor. The operations may be completed on each operand in one or more cycles through the circuitry of the ALU, and the path of the operands through the ALU may be based on the width of the ALU, the size of the operands, or the type of operation to be performed.
Abstract:
An internal processor of a memory device configured to selectively execute instructions in parallel. One such internal processor includes a plurality of arithmetic logic units (ALUs), each connected to conditional masking logic, and each configured to process conditional instructions. A condition instruction may be received by a sequencer of the memory device. Once the condition instruction is received, the sequencer may enable the conditional masking logic of the ALUs. The sequencer may toggle a signal to the conditional masking logic such that the masking logic masks certain instructions if a condition of the condition instruction has been met, and masks other instructions if the condition has not been met. In one embodiment, each ALU in the internal processor may selectively perform instructions in parallel.
Abstract:
Described herein are systems, methods, and apparatuses for device communication over IP. In some embodiments, IPv6 addresses are compressed into ISO/IEC 14908-1 addresses, and use leading zero suppression to compress the headers. In some embodiments, IPv4 the least significant two bytes of the IPv4 address are used as an ISO/IEC 14908-1 subnet and node number.
Abstract:
The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters.
Abstract:
The present invention concerns tunable distributed Bragg reflector (DBR) semiconductor lasers, in particular a DBR laser with a branched optical waveguide 5 within which a plurality of differently shaped lasing cavities may be formed, and a method of operation of such a laser. The laser may comprise a phase control section (418), gain section (420, 422), a sampled grating DBR (412) giving a comb-line spectrum and two tunable, chirped DBRs (414, 416) for broadband frequency training and a coupling section (410).
Abstract:
The production of purified water from a residential reverse osmosis drinking water system is limited by the pressure build up in the holding tank or reservoir. While the pressure in the tank increases the brine or waste water continues to flow at a constant rate. This condition makes an undesirable out of proportion relationship between the purified water and the waste water. The production of product water is controlled by the differential pressure across the purification membrane, as the tank pressure increases the differential pressure decreases and reduced production of product water results. The purpose of the device is to utilize the increasing tank pressure as a force to actuate the valve that proportions the waste water in a direct relationship with the product water. The ratio between the product water and the waste water remains constant during the period that purified water is being delivered to the holding tank.
Abstract:
Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in a system. The memory circuits may be stacked and may also be ranked memory circuits. The global memory select signal may be sent to a counter. Such a counter could count the length of time that the global memory select signal is active, and based on the counting, sends a count signal to a comparator. The comparator may compare the count signal with a programmed value to determine if a specific memory chip and/or port is to be accessed. This configuration may be duplicated over multiple ports on the same memory device, as well as across multiple memory ranks.
Abstract:
Volume adjustment based on listener position is disclosed. A position of one or more speakers is identified, and a position of a listener is tracked. For each of the one or more speakers, a changing distance between that speaker and the listener is assessed. A volume of that speaker is automatically adjusted in real-time based on a current distance between that speaker and the listener.