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    HIGH PERFORMANCE VERIFY TECHNIQUES IN A MEMORY DEVICE
    111.
    发明公开
    HIGH PERFORMANCE VERIFY TECHNIQUES IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240112744A1

    公开(公告)日：2024-04-04

    申请号：US17957606

    申请日：2022-09-30

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Wei Cao ,  Deepanshu Dutta

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10

    CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102

    Abstract: The memory device includes at least one memory block with a plurality of memory cells arranged in a plurality of word lines. The memory device includes control circuitry that is configured to program the memory cells of the at least one memory block in a plurality of program loops. The control circuitry is further configured to receive a command to write user data to the memory device. On at least a portion of a selected word line of the plurality of word lines, the control circuitry is configured to perform a smart verify operation to acquire a smart verify programming voltage. After the smart verify programming voltage is acquired, in a plurality of program loops, the control circuitry is configured to program the memory cells of the selected word line to include the user data and data that corresponds to the smart verify programming voltage.

    SEMI-CIRCLE DRAIN SIDE SELECT GATE MAINTENANCE BY SELECTIVE SEMI-CIRCLE DUMMY WORD LINE PROGRAM
    115.
    发明申请
    SEMI-CIRCLE DRAIN SIDE SELECT GATE MAINTENANCE BY SELECTIVE SEMI-CIRCLE DUMMY WORD LINE PROGRAM 有权

    公开(公告)号：US20230046677A1

    公开(公告)日：2023-02-16

    申请号：US17398718

    申请日：2021-08-10

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink ,  Shubhajit Mukherjee

    IPC: G11C16/14 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08 ,  G11C16/34 ,  G11C16/24

    Abstract: A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

    PROGRAM TAIL PLANE COMPARATOR FOR NON-VOLATILE MEMORY STRUCTURES
    117.
    发明申请
    PROGRAM TAIL PLANE COMPARATOR FOR NON-VOLATILE MEMORY STRUCTURES 有权

    公开(公告)号：US20220359023A1

    公开(公告)日：2022-11-10

    申请号：US17307285

    申请日：2021-05-04

    Applicant: SanDisk Technologies LLC

    Inventor： Fanqi Wu ,  Hua-Ling Hsu ,  Deepanshu Dutta ,  Huai-yuan Tseng

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C29/50

    Abstract: A method for detecting and isolating defective memory plane(s) of a non-volatile memory structure during a program verify operation, comprising: initiating, for each plane, a word line verify voltage level scan with a bit scan pass fail criterion and at a starting voltage located within an intended program threshold voltage distribution curve, incrementally decreasing the word line verify voltage by a predetermined offset until a specific condition of the scan is obtained, and storing the voltage at which the specific condition of the scan is obtained, wherein the stored voltage represents a voltage of an upper tail portion of an actual programmed threshold voltage distribution curve of the plane. The stored voltages of all of the memory planes of the structure are compared to determine which plane corresponds to the lowest stored voltage. A “fail” status is applied to the plane corresponding to the lowest stored voltage.

    SYSTEMS AND METHODS FOR DUAL-PULSE PROGRAMMING
    118.
    发明申请
    SYSTEMS AND METHODS FOR DUAL-PULSE PROGRAMMING 有权

    公开(公告)号：US20220208285A1

    公开(公告)日：2022-06-30

    申请号：US17137871

    申请日：2020-12-30

    Applicant: SanDisk Technologies LLC

    Inventor： Ravi Kumar ,  Deepanshu Dutta

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C16/24

    Abstract: A memory device comprising control circuitry configured to apply a first program voltage to a selected word line, wherein a first subset of memory cells of the selected word line, that correspond to a first set of data states, are inhibited from being programmed with the first program voltage, and wherein the first program voltage is applied to a second subset of memory cells corresponding to a second set of data states. The control circuitry is further configured to cause a first voltage of the selected word line to discharge to a second voltage level corresponding to a second program voltage such that the second program voltage is applied to at least the first subset of memory cells. The control circuitry is further configured to perform a verify operation to verify whether the first subset of memory cells and the second subset of memory cells have completed programming.

    Systems and methods for program verification on a memory system
    119.
    发明授权
    Systems and methods for program verification on a memory system 有权

    公开(公告)号：US11244735B2

    公开(公告)日：2022-02-08

    申请号：US16793749

    申请日：2020-02-18

    Applicant: SanDisk Technologies LLC

    Inventor： Zhiping Zhang ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

    IPC: G11C16/34 ,  G11C16/12 ,  G11C11/56 ,  G11C16/26

    Abstract: A method for memory program verification includes performing a write operation on memory cells of a memory device. The method also includes identifying memory strings associated with respective memory cells of the memory cells. The method also includes identifying a first memory string of the memory strings. The method also includes disabling a portion of a write verification for the first memory string. The method also includes enabling the portion of the write verification for other memory strings of the memory strings. The method also includes performing at least the portion of the write verification operation on write verification enabled memory strings.

    PEAK POWER REDUCTION MANAGEMENT IN NON-VOLATILE STORAGE BY DELAYING START TIMES OPERATIONS
    120.
    发明申请
    PEAK POWER REDUCTION MANAGEMENT IN NON-VOLATILE STORAGE BY DELAYING START TIMES OPERATIONS 有权

    公开(公告)号：US20210405920A1

    公开(公告)日：2021-12-30

    申请号：US16912381

    申请日：2020-06-25

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Mark Murin ,  Hua-Ling Cynthia Hsu ,  Tomer Eliash ,  Huai-Yuan Tseng ,  Deepanshu Dutta

    IPC: G06F3/06 ,  G11C16/10 ,  G11C16/32 ,  H01L25/065

    Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.

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