公开(公告)号：US11755813B2

公开(公告)日：2023-09-12

申请号：US17404594

申请日：2021-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Li-Chun Tien ,  Shun Li Chen ,  Lee-Chung Lu

IPC: G06F30/398 ,  H01L27/02 ,  H01L27/118 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881

Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

公开(公告)号：US11550986B2

公开(公告)日：2023-01-10

申请号：US17326811

申请日：2021-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pochun Wang ,  Yu-Jung Chang ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang

IPC: G06F30/392 ,  H01L27/092 ,  H03K19/0948 ,  H03K19/20 ,  H01L23/522 ,  H01L23/528 ,  G06F30/39

Abstract: An integrated circuit includes a first active region, a second active region, a first insulating region, a first contact and a second contact. The first and second active region extend in a first direction, are in a substrate, and are located on a first level. The second active region is separated from the first active region in a second direction. The first insulating region is over the first active region. The first contact extends in the second direction, overlaps the second active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first insulating region and the first contact. The second contact is electrically insulated from the first active region, and is located on a third level different from the first level and the second level.

公开(公告)号：US11417588B2

公开(公告)日：2022-08-16

申请号：US16943806

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Wei-Ren Chen ,  Chih-Liang Chen ,  Wei-Ling Chang ,  Hui-Zhong Zhuang ,  Li-Chun Tien

IPC: H01L23/48 ,  H01L21/48 ,  H01L27/02

Abstract: A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch.

公开(公告)号：US11302787B2

公开(公告)日：2022-04-12

申请号：US16580779

申请日：2019-09-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shang-Syuan Ciou ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Li-Chun Tien

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/78 ,  H01L29/08

Abstract: A semiconductor device includes an active region in a substrate. The active region extends in a first direction. The semiconductor device further includes a gate structure extending in a second direction different from the first direction. The gate structure extends across the active region. The semiconductor device further includes a plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure. A first source/drain contact of the plurality of source/drain contacts has a first width, and a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width.

公开(公告)号：US11281835B2

公开(公告)日：2022-03-22

申请号：US16860714

申请日：2020-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Sheng-Hsiung Wang ,  Hui-Zhong Zhuang ,  Yu-Cheng Yeh ,  Tsung-Chieh Tsai ,  Juing-Yi Wu ,  Liang-Yao Lee ,  Jyh-Kang Ting

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L27/02 ,  H01L27/118

Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

公开(公告)号：US20220084945A1

公开(公告)日：2022-03-17

申请号：US17021051

申请日：2020-09-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chun Tien ,  Chih-Liang Chen ,  Hui-Zhong Zhuang ,  Shun Li Chen ,  Ting Yu Chen

IPC: H01L23/528 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

公开(公告)号：US20210200927A1

公开(公告)日：2021-07-01

申请号：US16732206

申请日：2019-12-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheok-Kei Lei ,  Chi-Lin Liu ,  Yu-Lun Ou ,  Chien-Hsing Li ,  Zhe-Wei Jiang ,  Hui-Zhong Zhuang

IPC: G06F30/392 ,  H01L27/02 ,  H01L23/528 ,  G06F30/327

Abstract: A system and method for transistor placement in a standard cell layout includes identifying a plurality of transistors in a circuit. A drain terminal of each of the plurality of transistors is connected to an output of the circuit. The system and method also include determining that a first transistor and a second transistor of the plurality of transistors satisfy a merging priority, combining an active region of the first transistor and the second transistor to form a mega transistor having a common active region, and replacing the first transistor and the second transistor in the standard cell layout of the circuit with the mega transistor. The common active region combines the active region of a first drain terminal of the first transistor and a second drain terminal of the second transistor.

公开(公告)号：US11048849B2

公开(公告)日：2021-06-29

申请号：US16659270

申请日：2019-10-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Yu-Jung Chang

IPC: G06F30/392 ,  H01L27/092 ,  H03K19/0948 ,  H03K19/20 ,  H01L23/522 ,  H01L23/528 ,  G06F30/39

Abstract: An integrated circuit includes a first active region, a second active region, a third active region, a first contact and a second contact. The first active region and the second active region are separated from each other in a first direction, and are located on a first level. The third active region is located on the first level and is separated from the second active region in a second direction different from the first direction. The first contact extends in the second direction, overlaps the first active region, and is located on a second level different from the first level. The second contact extends in the first direction and the second direction, overlaps the first contact and the third active region, is electrically coupled to the first contact, and is located on a third level different from the first level and the second level.

公开(公告)号：US11031334B2

公开(公告)日：2021-06-08

申请号：US16563215

申请日：2019-09-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Sheng-Hsiung Wang

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/088 ,  H01L29/40 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485

Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.

公开(公告)号：US11004855B2

公开(公告)日：2021-05-11

申请号：US16515709

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Guo-Huei Wu ,  Yu-Jung Chang

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.