公开(公告)号：US20200273966A1

公开(公告)日：2020-08-27

申请号：US16870360

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Yen-Yu Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L21/762 ,  H01L21/285 ,  H01L21/768

Abstract: A semiconductor device includes a conductive feature over a substrate, a ruthenium-containing feature disposed over the conductive feature, and a first barrier layer disposed over the conductive feature and over sidewalls of the ruthenium-containing feature. The semiconductor device also includes a second barrier layer disposed over sidewalls of the first barrier layer, and a third barrier layer disposed over sidewalls of the second barrier layer. The first, second, and third barrier layers include different material compositions.

公开(公告)号：US10748806B2

公开(公告)日：2020-08-18

申请号：US16230765

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Yu Chen ,  Wei-Jen Chen ,  Yi-Chen Chiang ,  Tsang-Yang Liu ,  Chang-Sheng Lee ,  Wei-Chen Liao ,  Wei Zhang

IPC: H01L21/687

Abstract: A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.

公开(公告)号：US10651066B2

公开(公告)日：2020-05-12

申请号：US15879651

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Powen Huang ,  Yao-Yuan Shang ,  Kuo-Shu Tseng ,  Yen-Yu Chen ,  Chun-Chih Lin ,  Yi-Ming Dai

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/673 ,  H01L21/02 ,  G01D7/00 ,  G01D5/00 ,  B08B3/04

Abstract: A method for fault detection in a fabrication facility is provided. The method includes moving a wafer carrier using a transportation apparatus. The method further includes measuring an environmental condition within the wafer carrier or around the wafer carrier using a metrology tool positioned on the wafer carrier during the movement of the wafer carrier. The method also includes issuing a warning when the detected environmental condition is outside a range of acceptable values.

公开(公告)号：US10354965B2

公开(公告)日：2019-07-16

申请号：US15719370

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Chun-Chih Lin ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Chih-Wei Lin ,  Wen-Hao Cheng

IPC: H01L23/52 ,  H01L23/00

Abstract: The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.

公开(公告)号：US10345716B2

公开(公告)日：2019-07-09

申请号：US15877646

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Yuan Shang ,  Kuo-Shu Tseng ,  Yen-Yu Chen ,  Chun-Chih Lin ,  Yi-Ming Dai

IPC: G03F7/20

Abstract: A method for fault detection in a fabrication system is provided. The method includes transferring a reticle carrier containing a reticle from an original position to a destination position. The method further includes detecting environmental condition in the reticle carrier during the transfer of the reticle carrier using a metrology tool that is positioned at the reticle carrier. The method also includes issuing a warning when the detected environmental condition is outside a range of acceptable values.

公开(公告)号：US20190139828A1

公开(公告)日：2019-05-09

申请号：US16199498

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3213

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

公开(公告)号：US20190139759A1

公开(公告)日：2019-05-09

申请号：US15804575

申请日：2017-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Yen-Yu Chen

IPC: H01L21/02 ,  H01L21/28

Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

公开(公告)号：US20180350948A1

公开(公告)日：2018-12-06

申请号：US16050094

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Han-Wen Liao ,  Xuan-You Yan ,  Yen-Yu Chen ,  Chun-Chih Lin

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L21/32135 ,  H01L21/32137 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

公开(公告)号：US10074547B2

公开(公告)日：2018-09-11

申请号：US14135017

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Shu Tseng ,  You-Feng Chen ,  Yen-Yu Chen

IPC: H01L21/67

CPC classification number: H01L21/6715

Abstract: Embodiments of a photoresist supply system including a photoresist nozzle device are provided. The photoresist nozzle device includes a tube including a first segment, a curved segment connected to the first segment, and a second segment connected to the curved segment. The photoresist nozzle device also includes a nozzle connected to the second segment.

公开(公告)号：US09803274B2

公开(公告)日：2017-10-31

申请号：US14080561

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei Bih ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Hsien-Chieh Hsiao ,  Chang-Sheng Lee ,  Wei-Chen Liao ,  Wei Zhang

IPC: C23C14/35 ,  C23C14/34 ,  H01J37/34 ,  H01J37/32 ,  C23C14/56

CPC classification number: C23C14/34 ,  C23C14/564 ,  H01J37/32467 ,  H01J37/32477 ,  H01J37/34 ,  H01J37/3411 ,  H01J37/3426 ,  H01J37/3447

Abstract: A physical vapor deposition (PVD) chamber, a process kit of a PVD chamber and a method of fabricating a process kit of a PVD chamber are provided. In various embodiments, the PVD chamber includes a sputtering target, a power supply, a process kit, and a substrate support. The sputtering target has a sputtering surface that is in contact with a process region. The power supply is electrically connected to the sputtering target. The process kit has an inner surface at least partially enclosing the process region, and a liner layer disposed on the inner surface. The substrate support has a substrate receiving surface, wherein the liner layer disposed on the inner surface of the process kit has a surface roughness (Rz), and the surface roughness (Rz) is substantially in a range of 50-200 μm.